drm/radeon/r520.c

36 int r520_mc_wait_for_idle(struct radeon_device *rdev)
41 	for (i = 0; i < rdev->usec_timeout; i++) {
52 static void r520_gpu_init(struct radeon_device *rdev)
56 	rv515_vga_render_disable(rdev);
78 	if (rdev->family == CHIP_RV530) {
81 	r420_pipes_init(rdev);
88 	if (r520_mc_wait_for_idle(rdev)) {
93 static void r520_vram_get_type(struct radeon_device *rdev)
97 	rdev->mc.vram_width = 128;
98 	rdev->mc.vram_is_ddr = true;
102 		rdev->mc.vram_width = 32;
105 		rdev->mc.vram_width = 64;
108 		rdev->mc.vram_width = 128;
111 		rdev->mc.vram_width = 256;
114 		rdev->mc.vram_width = 128;
118 		rdev->mc.vram_width *= 2;
121 static void r520_mc_init(struct radeon_device *rdev)
124 	r520_vram_get_type(rdev);
125 	r100_vram_init_sizes(rdev);
126 	radeon_vram_location(rdev, &rdev->mc, 0);
127 	rdev->mc.gtt_base_align = 0;
128 	if (!(rdev->flags & RADEON_IS_AGP))
129 		radeon_gtt_location(rdev, &rdev->mc);
130 	radeon_update_bandwidth_info(rdev);
133 static void r520_mc_program(struct radeon_device *rdev)
138 	rv515_mc_stop(rdev, &save);
141 	if (r520_mc_wait_for_idle(rdev))
142 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
144 	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
147 			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
148 			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
150 		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
151 	if (rdev->flags & RADEON_IS_AGP) {
153 			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
154 			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
155 		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
157 			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
164 	rv515_mc_resume(rdev, &save);
167 static int r520_startup(struct radeon_device *rdev)
171 	r520_mc_program(rdev);
173 	rv515_clock_startup(rdev);
175 	r520_gpu_init(rdev);
178 	if (rdev->flags & RADEON_IS_PCIE) {
179 		r = rv370_pcie_gart_enable(rdev);
185 	r = radeon_wb_init(rdev);
189 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
191 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
196 	if (!rdev->irq.installed) {
197 		r = radeon_irq_kms_init(rdev);
202 	rs600_irq_set(rdev);
203 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
205 	r = r100_cp_init(rdev, 1024 * 1024);
207 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
211 	r = radeon_ib_pool_init(rdev);
213 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
220 int r520_resume(struct radeon_device *rdev)
225 	if (rdev->flags & RADEON_IS_PCIE)
226 		rv370_pcie_gart_disable(rdev);
228 	rv515_clock_startup(rdev);
230 	if (radeon_asic_reset(rdev)) {
231 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
236 	atom_asic_init(rdev->mode_info.atom_context);
238 	rv515_clock_startup(rdev);
240 	radeon_surface_init(rdev);
242 	rdev->accel_working = true;
243 	r = r520_startup(rdev);
245 		rdev->accel_working = false;
250 int r520_init(struct radeon_device *rdev)
255 	radeon_scratch_init(rdev);
257 	radeon_surface_init(rdev);
259 	r100_restore_sanity(rdev);
262 	if (!radeon_get_bios(rdev)) {
263 		if (ASIC_IS_AVIVO(rdev))
266 	if (rdev->is_atom_bios) {
267 		r = radeon_atombios_init(rdev);
271 		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
275 	if (radeon_asic_reset(rdev)) {
276 		dev_warn(rdev->dev,
282 	if (radeon_boot_test_post_card(rdev) == false)
285 	if (!radeon_card_posted(rdev) && rdev->bios) {
287 		atom_asic_init(rdev->mode_info.atom_context);
290 	radeon_get_clock_info(rdev->ddev);
292 	if (rdev->flags & RADEON_IS_AGP) {
293 		r = radeon_agp_init(rdev);
295 			radeon_agp_disable(rdev);
299 	r520_mc_init(rdev);
300 	rv515_debugfs(rdev);
302 	radeon_fence_driver_init(rdev);
304 	r = radeon_bo_init(rdev);
307 	r = rv370_pcie_gart_init(rdev);
310 	rv515_set_safe_registers(rdev);
313 	radeon_pm_init(rdev);
315 	rdev->accel_working = true;
316 	r = r520_startup(rdev);
319 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
320 		r100_cp_fini(rdev);
321 		radeon_wb_fini(rdev);
322 		radeon_ib_pool_fini(rdev);
323 		radeon_irq_kms_fini(rdev);
324 		rv370_pcie_gart_fini(rdev);
325 		radeon_agp_fini(rdev);
326 		rdev->accel_working = false;