Lines Matching defs:rdev
59 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
64 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
65 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
67 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
71 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
75 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
76 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
78 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
84 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
86 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
118 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
121 void __iomem *ptr = rdev->gart.ptr;
129 int rv370_pcie_gart_init(struct radeon_device *rdev)
133 if (rdev->gart.robj) {
138 r = radeon_gart_init(rdev);
141 rv370_debugfs_pcie_gart_info_init(rdev);
143 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
144 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
145 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
146 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
147 return radeon_gart_table_vram_alloc(rdev);
150 int rv370_pcie_gart_enable(struct radeon_device *rdev)
156 if (rdev->gart.robj == NULL) {
157 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
160 r = radeon_gart_table_vram_pin(rdev);
166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
167 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
171 table_addr = rdev->gart.table_addr;
174 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
182 rv370_pcie_gart_tlb_flush(rdev);
184 (unsigned)(rdev->mc.gtt_size >> 20),
186 rdev->gart.ready = true;
190 void rv370_pcie_gart_disable(struct radeon_device *rdev)
201 radeon_gart_table_vram_unpin(rdev);
204 void rv370_pcie_gart_fini(struct radeon_device *rdev)
206 radeon_gart_fini(rdev);
207 rv370_pcie_gart_disable(rdev);
208 radeon_gart_table_vram_free(rdev);
211 void r300_fence_ring_emit(struct radeon_device *rdev,
214 struct radeon_ring *ring = &rdev->ring[fence->ring];
234 radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
237 radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
239 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
245 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
252 switch (rdev->num_gb_pipes) {
268 r = radeon_ring_lock(rdev, ring, 64);
332 radeon_ring_unlock_commit(rdev, ring, false);
335 static void r300_errata(struct radeon_device *rdev)
337 rdev->pll_errata = 0;
339 if (rdev->family == CHIP_R300 &&
341 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
345 int r300_mc_wait_for_idle(struct radeon_device *rdev)
350 for (i = 0; i < rdev->usec_timeout; i++) {
361 static void r300_gpu_init(struct radeon_device *rdev)
365 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
366 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
368 rdev->num_gb_pipes = 2;
371 rdev->num_gb_pipes = 1;
373 rdev->num_z_pipes = 1;
375 switch (rdev->num_gb_pipes) {
392 if (r100_gui_wait_for_idle(rdev)) {
403 if (r100_gui_wait_for_idle(rdev)) {
406 if (r300_mc_wait_for_idle(rdev)) {
410 rdev->num_gb_pipes, rdev->num_z_pipes);
413 int r300_asic_reset(struct radeon_device *rdev, bool hard)
423 r100_mc_stop(rdev, &save);
425 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
434 pci_save_state(rdev->pdev);
436 r100_bm_disable(rdev);
444 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
456 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
458 pci_restore_state(rdev->pdev);
459 r100_enable_bm(rdev);
462 dev_err(rdev->dev, "failed to reset GPU\n");
465 dev_info(rdev->dev, "GPU reset succeed\n");
466 r100_mc_resume(rdev, &save);
473 void r300_mc_init(struct radeon_device *rdev)
479 rdev->mc.vram_is_ddr = true;
483 case 0: rdev->mc.vram_width = 64; break;
484 case 1: rdev->mc.vram_width = 128; break;
485 case 2: rdev->mc.vram_width = 256; break;
486 default: rdev->mc.vram_width = 128; break;
488 r100_vram_init_sizes(rdev);
489 base = rdev->mc.aper_base;
490 if (rdev->flags & RADEON_IS_IGP)
492 radeon_vram_location(rdev, &rdev->mc, base);
493 rdev->mc.gtt_base_align = 0;
494 if (!(rdev->flags & RADEON_IS_AGP))
495 radeon_gtt_location(rdev, &rdev->mc);
496 radeon_update_bandwidth_info(rdev);
499 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
503 if (rdev->flags & RADEON_IS_IGP)
506 if (!(rdev->flags & RADEON_IS_PCIE))
558 int rv370_get_pcie_lanes(struct radeon_device *rdev)
562 if (rdev->flags & RADEON_IS_IGP)
565 if (!(rdev->flags & RADEON_IS_PCIE))
592 struct radeon_device *rdev = m->private;
615 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
618 struct dentry *root = rdev->ddev->primary->debugfs_root;
620 debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
746 if (p->rdev->family < CHIP_RV515)
753 if (p->rdev->family < CHIP_RV515) {
762 p->rdev->cmask_filp != p->filp) {
812 if (p->rdev->family < CHIP_RV515) {
962 if (p->rdev->family < CHIP_R420) {
1029 if (p->rdev->family >= CHIP_RV515) {
1096 if (p->rdev->hyperz_filp != p->filp) {
1106 if (p->rdev->hyperz_filp != p->filp) {
1144 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1148 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1151 if (p->rdev->family >= CHIP_RV350)
1157 if (p->rdev->family == CHIP_RV530)
1213 r = r100_cs_track_check(p->rdev, track);
1228 r = r100_cs_track_check(p->rdev, track);
1235 r = r100_cs_track_check(p->rdev, track);
1242 r = r100_cs_track_check(p->rdev, track);
1249 r = r100_cs_track_check(p->rdev, track);
1256 r = r100_cs_track_check(p->rdev, track);
1263 if (p->rdev->hyperz_filp != p->filp)
1267 if (p->rdev->cmask_filp != p->filp)
1288 r100_cs_track_clear(p->rdev, track);
1299 p->rdev->config.r300.reg_safe_bm,
1300 p->rdev->config.r300.reg_safe_bm_size,
1319 void r300_set_reg_safe(struct radeon_device *rdev)
1321 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1322 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1325 void r300_mc_program(struct radeon_device *rdev)
1329 r100_debugfs_mc_info_init(rdev);
1332 r100_mc_stop(rdev, &save);
1333 if (rdev->flags & RADEON_IS_AGP) {
1335 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1336 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1337 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1339 upper_32_bits(rdev->mc.agp_base) & 0xff);
1346 if (r300_mc_wait_for_idle(rdev))
1350 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1351 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1352 r100_mc_resume(rdev, &save);
1355 void r300_clock_startup(struct radeon_device *rdev)
1360 radeon_legacy_set_clock_gating(rdev, 1);
1364 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1369 static int r300_startup(struct radeon_device *rdev)
1374 r100_set_common_regs(rdev);
1376 r300_mc_program(rdev);
1378 r300_clock_startup(rdev);
1380 r300_gpu_init(rdev);
1383 if (rdev->flags & RADEON_IS_PCIE) {
1384 r = rv370_pcie_gart_enable(rdev);
1389 if (rdev->family == CHIP_R300 ||
1390 rdev->family == CHIP_R350 ||
1391 rdev->family == CHIP_RV350)
1392 r100_enable_bm(rdev);
1394 if (rdev->flags & RADEON_IS_PCI) {
1395 r = r100_pci_gart_enable(rdev);
1401 r = radeon_wb_init(rdev);
1405 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1407 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1412 if (!rdev->irq.installed) {
1413 r = radeon_irq_kms_init(rdev);
1418 r100_irq_set(rdev);
1419 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1421 r = r100_cp_init(rdev, 1024 * 1024);
1423 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1427 r = radeon_ib_pool_init(rdev);
1429 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1436 int r300_resume(struct radeon_device *rdev)
1441 if (rdev->flags & RADEON_IS_PCIE)
1442 rv370_pcie_gart_disable(rdev);
1443 if (rdev->flags & RADEON_IS_PCI)
1444 r100_pci_gart_disable(rdev);
1446 r300_clock_startup(rdev);
1448 if (radeon_asic_reset(rdev)) {
1449 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1454 radeon_combios_asic_init(rdev->ddev);
1456 r300_clock_startup(rdev);
1458 radeon_surface_init(rdev);
1460 rdev->accel_working = true;
1461 r = r300_startup(rdev);
1463 rdev->accel_working = false;
1468 int r300_suspend(struct radeon_device *rdev)
1470 radeon_pm_suspend(rdev);
1471 r100_cp_disable(rdev);
1472 radeon_wb_disable(rdev);
1473 r100_irq_disable(rdev);
1474 if (rdev->flags & RADEON_IS_PCIE)
1475 rv370_pcie_gart_disable(rdev);
1476 if (rdev->flags & RADEON_IS_PCI)
1477 r100_pci_gart_disable(rdev);
1481 void r300_fini(struct radeon_device *rdev)
1483 radeon_pm_fini(rdev);
1484 r100_cp_fini(rdev);
1485 radeon_wb_fini(rdev);
1486 radeon_ib_pool_fini(rdev);
1487 radeon_gem_fini(rdev);
1488 if (rdev->flags & RADEON_IS_PCIE)
1489 rv370_pcie_gart_fini(rdev);
1490 if (rdev->flags & RADEON_IS_PCI)
1491 r100_pci_gart_fini(rdev);
1492 radeon_agp_fini(rdev);
1493 radeon_irq_kms_fini(rdev);
1494 radeon_fence_driver_fini(rdev);
1495 radeon_bo_fini(rdev);
1496 radeon_atombios_fini(rdev);
1497 kfree(rdev->bios);
1498 rdev->bios = NULL;
1501 int r300_init(struct radeon_device *rdev)
1506 r100_vga_render_disable(rdev);
1508 radeon_scratch_init(rdev);
1510 radeon_surface_init(rdev);
1513 r100_restore_sanity(rdev);
1515 if (!radeon_get_bios(rdev)) {
1516 if (ASIC_IS_AVIVO(rdev))
1519 if (rdev->is_atom_bios) {
1520 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1523 r = radeon_combios_init(rdev);
1528 if (radeon_asic_reset(rdev)) {
1529 dev_warn(rdev->dev,
1535 if (radeon_boot_test_post_card(rdev) == false)
1538 r300_errata(rdev);
1540 radeon_get_clock_info(rdev->ddev);
1542 if (rdev->flags & RADEON_IS_AGP) {
1543 r = radeon_agp_init(rdev);
1545 radeon_agp_disable(rdev);
1549 r300_mc_init(rdev);
1551 radeon_fence_driver_init(rdev);
1553 r = radeon_bo_init(rdev);
1556 if (rdev->flags & RADEON_IS_PCIE) {
1557 r = rv370_pcie_gart_init(rdev);
1561 if (rdev->flags & RADEON_IS_PCI) {
1562 r = r100_pci_gart_init(rdev);
1566 r300_set_reg_safe(rdev);
1569 radeon_pm_init(rdev);
1571 rdev->accel_working = true;
1572 r = r300_startup(rdev);
1575 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1576 r100_cp_fini(rdev);
1577 radeon_wb_fini(rdev);
1578 radeon_ib_pool_fini(rdev);
1579 radeon_irq_kms_fini(rdev);
1580 if (rdev->flags & RADEON_IS_PCIE)
1581 rv370_pcie_gart_fini(rdev);
1582 if (rdev->flags & RADEON_IS_PCI)
1583 r100_pci_gart_fini(rdev);
1584 radeon_agp_fini(rdev);
1585 rdev->accel_working = false;