drm/radeon/cypress_dpm.c

403 					  struct atom_voltage_table *table,
408 	for (i = 0; i < table->count; i++) {
409 		if (value <= table->entries[i].value) {
411 			voltage->value = cpu_to_be16(table->entries[i].value);
416 	if (i == table->count)
1239 				       RV770_SMC_STATETABLE *table)
1246 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1248 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1250 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1252 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1254 	table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1256 	table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1259 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1261 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1264 	table->initialState.levels[0].mclk.mclk770.mclk_value =
1267 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1269 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1271 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1273 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1275 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1278 	table->initialState.levels[0].sclk.sclk_value =
1281 	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1283 	table->initialState.levels[0].ACIndex = 0;
1288 				       &table->initialState.levels[0].vddc);
1294 					       &table->initialState.levels[0].vddci);
1297 					    &table->initialState.levels[0].mvdd);
1300 	table->initialState.levels[0].aT = cpu_to_be32(a_t);
1302 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1306 		table->initialState.levels[0].gen2PCIE = 1;
1308 		table->initialState.levels[0].gen2PCIE = 0;
1310 		table->initialState.levels[0].gen2XSP = 1;
1312 		table->initialState.levels[0].gen2XSP = 0;
1315 		table->initialState.levels[0].strobeMode =
1320 			table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1322 			table->initialState.levels[0].mcFlags =  0;
1325 	table->initialState.levels[1] = table->initialState.levels[0];
1326 	table->initialState.levels[2] = table->initialState.levels[0];
1328 	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1334 				    RV770_SMC_STATETABLE *table)
1357 	table->ACPIState = table->initialState;
1359 	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1365 					       &table->ACPIState.levels[0].vddc);
1368 				table->ACPIState.levels[0].gen2PCIE = 1;
1370 				table->ACPIState.levels[0].gen2PCIE = 0;
1372 			table->ACPIState.levels[0].gen2PCIE = 0;
1374 			table->ACPIState.levels[0].gen2XSP = 1;
1376 			table->ACPIState.levels[0].gen2XSP = 0;
1381 					       &table->ACPIState.levels[0].vddc);
1382 		table->ACPIState.levels[0].gen2PCIE = 0;
1390 						       &table->ACPIState.levels[0].vddci);
1436 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1438 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1440 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1442 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1444 	table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1446 	table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1448 	table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1450 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1452 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1454 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1457 	table->ACPIState.levels[0].sclk.sclk_value = 0;
1459 	cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1462 		table->ACPIState.levels[0].ACIndex = 1;
1464 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
1465 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
1516 					       RV770_SMC_STATETABLE *table)
1521 		table->highSMIO[i] = 0;
1522 		table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1527 					RV770_SMC_STATETABLE *table)
1536 						   table);
1538 		table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1539 		table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1545 				table->maxVDDCIndexInPPTable = i;
1554 						   table);
1556 		table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1557 		table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1618 	RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1621 	memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1623 	cypress_populate_smc_voltage_tables(rdev, table);
1628 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1631 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1634 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1639 		table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1642 		table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1645 		table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1648 		table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1650 	ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1654 	ret = cypress_populate_smc_acpi_state(rdev, table);
1658 	table->driverState = table->initialState;
1662 				       (u8 *)table, sizeof(RV770_SMC_STATETABLE),