drm/radeon/atombios_encoders.c

553 	LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
601 			args.v1.ucMisc = 0;
602 			args.v1.ucAction = action;
604 				args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
605 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
608 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
610 					args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
613 					args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
615 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
617 				args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
824 	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
877 			args.v1.ucAction = action;
878 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
882 				args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
884 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
885 				args.v1.ucLaneNum = dp_lane_count;
887 				args.v1.ucLaneNum = 8;
889 				args.v1.ucLaneNum = 4;
893 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
897 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
900 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
904 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
906 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
908 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
909 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
929 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
953 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
955 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
957 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
959 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
993 	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1078 			args.v1.ucAction = action;
1080 				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1082 				args.v1.asMode.ucLaneSel = lane_num;
1083 				args.v1.asMode.ucLaneSet = lane_set;
1086 					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1088 					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1090 					args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1093 			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1096 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1098 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1105 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1107 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1109 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1111 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1114 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1116 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1121 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1123 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1126 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1129 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1131 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1398 	args.v1.ucAction = action;
1418 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1469 			args.v1.sDigEncoder.ucAction = action;
1470 			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1471 			args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1473 			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1475 					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1476 				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1478 				args.v1.sDigEncoder.ucLaneNum = 8;
1480 				args.v1.sDigEncoder.ucLaneNum = 4;
1840 	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1867 				args.v1.ucCRTC = radeon_crtc->crtc_id;
1870 					args.v1.ucCRTC = radeon_crtc->crtc_id;
1872 					args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1877 				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1882 					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1884 					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1889 				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1894 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1896 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1898 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1903 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1905 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1907 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;