drm/radeon/atombios_crtc.c

447 				     struct radeon_atom_ss *ss)
454 		/* Don't mess with SS if percentage is 0 or external ss.
459 		if (ss->percentage == 0)
461 		if (ss->type & ATOM_EXTERNAL_SS_MASK)
482 		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
496 		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
497 		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
500 		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
501 		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
515 		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
516 		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
519 		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
520 		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
521 		args.v1.ucSpreadSpectrumStep = ss->step;
522 		args.v1.ucSpreadSpectrumDelay = ss->delay;
523 		args.v1.ucSpreadSpectrumRange = ss->range;
527 		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
528 		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
532 		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
533 		args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
534 		args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
535 		args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
536 		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
543 		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
544 		args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
545 		args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
546 		args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
619 	/* use recommended ref_div for ss */
622 			if (radeon_crtc->ss.refdiv) {
624 				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
690 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
703 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
827 				      struct radeon_atom_ss *ss)
877 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
890 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
919 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
989 					radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
996 										 &radeon_crtc->ss,
1001 											 &radeon_crtc->ss,
1006 										 &radeon_crtc->ss,
1017 									 &radeon_crtc->ss,
1023 									 &radeon_crtc->ss,
1030 									 &radeon_crtc->ss,
1038 									 &radeon_crtc->ss,
1103 				 radeon_crtc->crtc_id, &radeon_crtc->ss);
1108 				  radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1111 		/* calculate ss amount and step size */
1115 				      (u32)radeon_crtc->ss.percentage) /
1116 				(100 * (u32)radeon_crtc->ss.percentage_divider);
1117 			radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1118 			radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1120 			if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1121 				step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1124 				step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1126 			radeon_crtc->ss.step = step_size;
1130 					 radeon_crtc->crtc_id, &radeon_crtc->ss);
2026 		struct radeon_atom_ss ss;
2027 		bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2031 			atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2035 			atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2149 	struct radeon_atom_ss ss;
2192 					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2201 						  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);