drm/radeon/atombios_crtc.c

1383 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1385 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1387 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1389 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1391 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1393 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1394 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1401 	WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1408 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1409 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1410 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1411 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1412 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1413 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1416 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1417 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1420 		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1423 		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1427 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1434 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1438 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1597 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1608 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1611 	       radeon_crtc->crtc_offset, (u32) fb_location);
1612 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1614 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1617 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1623 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1624 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1625 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1626 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1627 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1628 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1631 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1632 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1634 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1638 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1642 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1646 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
2168 		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2170 		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2234 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2237 			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2240 			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2243 			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2246 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2249 			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2254 			radeon_crtc->crtc_offset =
2257 			radeon_crtc->crtc_offset = 0;