Lines Matching refs:args
45 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
49 memset(&args, 0, sizeof(args));
51 args.ucCRTC = radeon_crtc->crtc_id;
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
65 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
66 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
68 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
69 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
88 ENABLE_SCALER_PS_ALLOCATION args;
105 memset(&args, 0, sizeof(args));
107 args.ucScaler = radeon_crtc->crtc_id;
113 args.ucTVStandard = ATOM_TV_NTSC;
116 args.ucTVStandard = ATOM_TV_PAL;
119 args.ucTVStandard = ATOM_TV_PALM;
122 args.ucTVStandard = ATOM_TV_PAL60;
125 args.ucTVStandard = ATOM_TV_NTSCJ;
128 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 args.ucTVStandard = ATOM_TV_SECAM;
134 args.ucTVStandard = ATOM_TV_PALCN;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
139 args.ucTVStandard = ATOM_TV_CV;
140 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
144 args.ucEnable = ATOM_SCALER_EXPANSION;
147 args.ucEnable = ATOM_SCALER_CENTER;
150 args.ucEnable = ATOM_SCALER_EXPANSION;
154 args.ucEnable = ATOM_SCALER_DISABLE;
156 args.ucEnable = ATOM_SCALER_CENTER;
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
174 ENABLE_CRTC_PS_ALLOCATION args;
176 memset(&args, 0, sizeof(args));
178 args.ucCRTC = radeon_crtc->crtc_id;
179 args.ucEnable = lock;
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
190 ENABLE_CRTC_PS_ALLOCATION args;
192 memset(&args, 0, sizeof(args));
194 args.ucCRTC = radeon_crtc->crtc_id;
195 args.ucEnable = state;
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
206 ENABLE_CRTC_PS_ALLOCATION args;
208 memset(&args, 0, sizeof(args));
210 args.ucCRTC = radeon_crtc->crtc_id;
211 args.ucEnable = state;
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
232 BLANK_CRTC_PS_ALLOCATION args;
235 memset(&args, 0, sizeof(args));
242 args.ucCRTC = radeon_crtc->crtc_id;
243 args.ucBlanking = state;
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
257 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
259 memset(&args, 0, sizeof(args));
261 args.ucDispPipeId = radeon_crtc->crtc_id;
262 args.ucEnable = state;
264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
308 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
312 memset(&args, 0, sizeof(args));
313 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
314 args.usH_Blanking_Time =
316 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
317 args.usV_Blanking_Time =
319 args.usH_SyncOffset =
321 args.usH_SyncWidth =
323 args.usV_SyncOffset =
325 args.usV_SyncWidth =
327 args.ucH_Border = radeon_crtc->h_border;
328 args.ucV_Border = radeon_crtc->v_border;
343 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
344 args.ucCRTC = radeon_crtc->crtc_id;
346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
355 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
359 memset(&args, 0, sizeof(args));
360 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
361 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
362 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
363 args.usH_SyncWidth =
365 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
366 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
367 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
368 args.usV_SyncWidth =
371 args.ucOverscanRight = radeon_crtc->h_border;
372 args.ucOverscanLeft = radeon_crtc->h_border;
373 args.ucOverscanBottom = radeon_crtc->v_border;
374 args.ucOverscanTop = radeon_crtc->v_border;
389 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
390 args.ucCRTC = radeon_crtc->crtc_id;
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
451 union atom_enable_ss args;
478 memset(&args, 0, sizeof(args));
481 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
482 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
485 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
488 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
491 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
496 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
497 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
498 args.v3.ucEnable = enable;
500 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
501 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
504 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
507 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
510 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
515 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
516 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
517 args.v2.ucEnable = enable;
519 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
520 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
521 args.v1.ucSpreadSpectrumStep = ss->step;
522 args.v1.ucSpreadSpectrumDelay = ss->delay;
523 args.v1.ucSpreadSpectrumRange = ss->range;
524 args.v1.ucPpll = pll_id;
525 args.v1.ucEnable = enable;
532 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
533 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
534 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
535 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
536 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
537 args.lvds_ss_2.ucEnable = enable;
543 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
544 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
545 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
547 args.lvds_ss.ucEnable = enable;
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
671 union adjust_pixel_clock args;
680 memset(&args, 0, sizeof(args));
687 args.v1.usPixelClock = cpu_to_le16(clock / 10);
688 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
689 args.v1.ucEncodeMode = encoder_mode;
691 args.v1.ucConfig |=
695 index, (uint32_t *)&args, sizeof(args));
696 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
699 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
700 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
701 args.v3.sInput.ucEncodeMode = encoder_mode;
702 args.v3.sInput.ucDispPllConfig = 0;
704 args.v3.sInput.ucDispPllConfig |=
707 args.v3.sInput.ucDispPllConfig |=
710 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
714 args.v3.sInput.ucDispPllConfig |=
717 args.v3.sInput.ucDispPllConfig |=
722 args.v3.sInput.ucExtTransmitterID =
725 args.v3.sInput.ucExtTransmitterID = 0;
728 index, (uint32_t *)&args, sizeof(args));
729 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
730 if (args.v3.sOutput.ucRefDiv) {
733 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
735 if (args.v3.sOutput.ucPostDiv) {
738 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
771 union set_pixel_clock args;
773 memset(&args, 0, sizeof(args));
787 args.v5.ucCRTC = ATOM_CRTC_INVALID;
788 args.v5.usPixelClock = cpu_to_le16(dispclk);
789 args.v5.ucPpll = ATOM_DCPLL;
795 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
797 args.v6.ucPpll = ATOM_EXT_PLL1;
799 args.v6.ucPpll = ATOM_PPLL0;
801 args.v6.ucPpll = ATOM_DCPLL;
812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
833 union set_pixel_clock args;
835 memset(&args, 0, sizeof(args));
847 args.v1.usPixelClock = cpu_to_le16(clock / 10);
848 args.v1.usRefDiv = cpu_to_le16(ref_div);
849 args.v1.usFbDiv = cpu_to_le16(fb_div);
850 args.v1.ucFracFbDiv = frac_fb_div;
851 args.v1.ucPostDiv = post_div;
852 args.v1.ucPpll = pll_id;
853 args.v1.ucCRTC = crtc_id;
854 args.v1.ucRefDivSrc = 1;
857 args.v2.usPixelClock = cpu_to_le16(clock / 10);
858 args.v2.usRefDiv = cpu_to_le16(ref_div);
859 args.v2.usFbDiv = cpu_to_le16(fb_div);
860 args.v2.ucFracFbDiv = frac_fb_div;
861 args.v2.ucPostDiv = post_div;
862 args.v2.ucPpll = pll_id;
863 args.v2.ucCRTC = crtc_id;
864 args.v2.ucRefDivSrc = 1;
867 args.v3.usPixelClock = cpu_to_le16(clock / 10);
868 args.v3.usRefDiv = cpu_to_le16(ref_div);
869 args.v3.usFbDiv = cpu_to_le16(fb_div);
870 args.v3.ucFracFbDiv = frac_fb_div;
871 args.v3.ucPostDiv = post_div;
872 args.v3.ucPpll = pll_id;
874 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
876 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
878 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
879 args.v3.ucTransmitterId = encoder_id;
880 args.v3.ucEncoderMode = encoder_mode;
883 args.v5.ucCRTC = crtc_id;
884 args.v5.usPixelClock = cpu_to_le16(clock / 10);
885 args.v5.ucRefDiv = ref_div;
886 args.v5.usFbDiv = cpu_to_le16(fb_div);
887 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
888 args.v5.ucPostDiv = post_div;
889 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
891 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
896 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
900 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
904 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
908 args.v5.ucTransmitterID = encoder_id;
909 args.v5.ucEncoderMode = encoder_mode;
910 args.v5.ucPpll = pll_id;
913 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
914 args.v6.ucRefDiv = ref_div;
915 args.v6.usFbDiv = cpu_to_le16(fb_div);
916 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
917 args.v6.ucPostDiv = post_div;
918 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
920 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
925 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
928 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
931 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
934 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
938 args.v6.ucTransmitterID = encoder_id;
939 args.v6.ucEncoderMode = encoder_mode;
940 args.v6.ucPpll = pll_id;
952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));