drm/radeon/atombios_crtc.c

440 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
481 		args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
482 		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
485 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
488 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
491 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
496 		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
497 		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
498 		args.v3.ucEnable = enable;
554 	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
699 				args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
700 				args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
701 				args.v3.sInput.ucEncodeMode = encoder_mode;
702 				args.v3.sInput.ucDispPllConfig = 0;
704 					args.v3.sInput.ucDispPllConfig |=
707 					args.v3.sInput.ucDispPllConfig |=
710 					args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
714 						args.v3.sInput.ucDispPllConfig |=
717 						args.v3.sInput.ucDispPllConfig |=
722 					args.v3.sInput.ucExtTransmitterID =
725 					args.v3.sInput.ucExtTransmitterID = 0;
729 				adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
730 				if (args.v3.sOutput.ucRefDiv) {
733 					radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
735 				if (args.v3.sOutput.ucPostDiv) {
738 					radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
758 	PIXEL_CLOCK_PARAMETERS_V3 v3;
867 			args.v3.usPixelClock = cpu_to_le16(clock / 10);
868 			args.v3.usRefDiv = cpu_to_le16(ref_div);
869 			args.v3.usFbDiv = cpu_to_le16(fb_div);
870 			args.v3.ucFracFbDiv = frac_fb_div;
871 			args.v3.ucPostDiv = post_div;
872 			args.v3.ucPpll = pll_id;
874 				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
876 				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
878 				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
879 			args.v3.ucTransmitterId = encoder_id;
880 			args.v3.ucEncoderMode = encoder_mode;