Lines Matching defs:ULONG
45 #ifndef ULONG
46 typedef unsigned long ULONG;
397 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
399 ULONG ulClockFreq:24;
401 ULONG ulClockFreq:24;
402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
403 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
410 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
419 ULONG ulClock; //When return, [23:0] return real clock
444 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
448 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
463 ULONG ulClockParams; //ULONG access for BE
483 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
484 ULONG ulClock:24; //Input= target clock, output = actual clock
486 ULONG ulClock:24; //Input= target clock, output = actual clock
487 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
496 ULONG ulClockParams; //ULONG access for BE
513 ULONG ulReserved[2];
543 ULONG ulClock;
569 ULONG ulReserved[2];
575 ULONG ulMemoryClock;
576 ULONG ulReserved;
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
668 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1398 ULONG ulReserved[2];
1657 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1672 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1674 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1677 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1679 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1688 ULONG ulDispEngClkFreq; // dispclk frequency
1705 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1782 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2002 ULONG ulTargetMemoryClock; //In 10Khz unit
2272 ULONG ulReserved;
2278 ULONG ulVotlageGpioState;
2279 ULONG ulVoltageGPioMask;
2287 ULONG ulReseved;
2311 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2322 ULONG ulReseved;
2402 ULONG ulSignature; // HW info table signature string "$ATI"
2415 ULONG ulSignature; // MM info table signature sting "$MMT"
2509 ULONG ulFirmwareRevision;
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2521 ULONG aulReservedForBIOS[3]; //Don't use them
2543 ULONG ulFirmwareRevision;
2544 ULONG ulDefaultEngineClock; //In 10Khz unit
2545 ULONG ulDefaultMemoryClock; //In 10Khz unit
2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2551 ULONG ulASICMaxEngineClock; //In 10Khz unit
2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2556 ULONG aulReservedForBIOS[2]; //Don't use them
2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2579 ULONG ulFirmwareRevision;
2580 ULONG ulDefaultEngineClock; //In 10Khz unit
2581 ULONG ulDefaultMemoryClock; //In 10Khz unit
2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2587 ULONG ulASICMaxEngineClock; //In 10Khz unit
2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2592 ULONG aulReservedForBIOS; //Don't use them
2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2616 ULONG ulFirmwareRevision;
2617 ULONG ulDefaultEngineClock; //In 10Khz unit
2618 ULONG ulDefaultMemoryClock; //In 10Khz unit
2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2624 ULONG ulASICMaxEngineClock; //In 10Khz unit
2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2655 ULONG ulFirmwareRevision;
2656 ULONG ulDefaultEngineClock; //In 10Khz unit
2657 ULONG ulDefaultMemoryClock; //In 10Khz unit
2658 ULONG ulReserved1;
2659 ULONG ulReserved2;
2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2663 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2670 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2696 ULONG ulFirmwareRevision;
2697 ULONG ulDefaultEngineClock; //In 10Khz unit
2698 ULONG ulDefaultMemoryClock; //In 10Khz unit
2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2701 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2702 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2704 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2705 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2711 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2715 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2716 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2729 ULONG ulReserved10[3]; // New added comparing to previous version
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2759 ULONG ulReserved[2];
2822 ULONG ulBootUpEngineClock; //in 10kHz unit
2823 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2824 ULONG ulBootUpUMAClock; //in 10kHz unit
2825 ULONG ulBootUpSidePortClock; //in 10kHz unit
2826 ULONG ulMinSidePortClock; //in 10kHz unit
2827 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2828 ULONG ulSystemConfig; //see explanation below
2829 ULONG ulBootUpReqDisplayVector;
2830 ULONG ulOtherDisplayMisc;
2831 ULONG ulDDISlot1Config;
2832 ULONG ulDDISlot2Config;
2837 ULONG ulDockingPinCFGInfo;
2838 ULONG ulCPUCapInfo;
2843 ULONG ulHTLinkFreq; //in 10Khz
2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2858 ULONG ulReserved3[96]; //must be 0x0
2995 ULONG ulBootUpEngineClock; //in 10kHz unit
2996 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2997 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2998 ULONG ulBootUpUMAClock; //in 10kHz unit
2999 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3000 ULONG ulBootUpReqDisplayVector;
3001 ULONG ulOtherDisplayMisc;
3002 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3003 ULONG ulSystemConfig; //TBD
3004 ULONG ulCPUCapInfo; //TBD
3010 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3011 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3012 ULONG ulDDISlot2Config;
3013 ULONG ulDDISlot3Config;
3014 ULONG ulDDISlot4Config;
3015 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3019 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3020 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3021 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3022 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3023 ULONG ulReserved6[61]; //must be 0x0
3507 ULONG ulReserved0;
3545 ULONG ulReserved[2];
3850 ULONG ulStartAddrUsedByFirmware;
3864 ULONG ulStartAddrUsedByFirmware;
4226 ULONG ulACPIDeviceEnum; //Reserved for now
4326 ULONG ulStrengthControl; // DVOA strength control for CF
4584 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4602 ULONG ulReserved;
4617 ULONG ulGpioMaskVal; // GPIO Mask value
4627 ULONG ulMaxVoltageLevel;
4644 ULONG ulReserved;
4699 ULONG ulEvvDerateTdp;
4700 ULONG ulEvvDerateTdc;
4701 ULONG ulBoardCoreTemp;
4702 ULONG ulMaxVddc;
4703 ULONG ulMinVddc;
4704 ULONG ulLoadLineSlop;
4705 ULONG ulLeakageTemp;
4706 ULONG ulLeakageVoltage;
4707 ULONG ulCACmEncodeRange;
4708 ULONG ulCACmEncodeAverage;
4709 ULONG ulCACbEncodeRange;
4710 ULONG ulCACbEncodeAverage;
4711 ULONG ulKt_bEncodeRange;
4712 ULONG ulKt_bEncodeAverage;
4713 ULONG ulKv_mEncodeRange;
4714 ULONG ulKv_mEncodeAverage;
4715 ULONG ulKv_bEncodeRange;
4716 ULONG ulKv_bEncodeAverage;
4717 ULONG ulLkgEncodeLn_MaxDivMin;
4718 ULONG ulLkgEncodeMin;
4719 ULONG ulEfuseLogisticAlpha;
4774 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4775 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4780 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4792 ULONG ulBootUpEngineClock;
4793 ULONG ulDentistVCOFreq;
4794 ULONG ulBootUpUMAClock;
4796 ULONG ulBootUpReqDisplayVector;
4797 ULONG ulOtherDisplayMisc;
4798 ULONG ulGPUCapInfo;
4799 ULONG ulSB_MMIO_Base_Addr;
4803 ULONG ulMinEngineClock;
4804 ULONG ulSystemConfig;
4805 ULONG ulCPUCapInfo;
4813 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
4814 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
4815 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
4817 ULONG ulGMCRestoreResetTime;
4818 ULONG ulMinimumNClk;
4819 ULONG ulIdleNClk;
4820 ULONG ulDDR_DLL_PowerUpTime;
4821 ULONG ulDDR_PLL_PowerUpTime;
4830 ULONG SclkDpmBoostMargin;
4831 ULONG SclkDpmThrottleMargin;
4834 ULONG ulBoostEngineCLock;
4841 ULONG ulReserved3[15];
4955 ULONG ulPowerplayTable[128];
4962 ULONG uReserved:2;
4963 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
4964 ULONG uCTDP_Value:14; // Override value in tens of milli watts
4965 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4967 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4968 ULONG uCTDP_Value:14; // Override value in tens of milli watts
4969 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
4970 ULONG uReserved:2;
4977 ULONG TDP_config_all;
4990 ULONG ulBootUpEngineClock;
4991 ULONG ulDentistVCOFreq;
4992 ULONG ulBootUpUMAClock;
4994 ULONG ulBootUpReqDisplayVector;
4995 ULONG ulOtherDisplayMisc;
4996 ULONG ulGPUCapInfo;
4997 ULONG ulSB_MMIO_Base_Addr;
5001 ULONG ulMinEngineClock;
5002 ULONG ulSystemConfig;
5003 ULONG ulCPUCapInfo;
5013 ULONG ulReserved[19];
5015 ULONG ulGMCRestoreResetTime;
5016 ULONG ulMinimumNClk;
5017 ULONG ulIdleNClk;
5018 ULONG ulDDR_DLL_PowerUpTime;
5019 ULONG ulDDR_PLL_PowerUpTime;
5028 ULONG SclkDpmBoostMargin;
5029 ULONG SclkDpmThrottleMargin;
5032 ULONG ulBoostEngineCLock;
5047 ULONG ulLCDBitDepthControlVal;
5048 ULONG ulNbpStateMemclkFreq[4];
5051 ULONG ulNbpStateNClkFreq[4];
5217 ULONG ulBootUpEngineClock;
5218 ULONG ulDentistVCOFreq;
5219 ULONG ulBootUpUMAClock;
5221 ULONG ulBootUpReqDisplayVector;
5222 ULONG ulVBIOSMisc;
5223 ULONG ulGPUCapInfo;
5224 ULONG ulDISP_CLK2Freq;
5228 ULONG ulReserved2;
5229 ULONG ulSystemConfig;
5230 ULONG ulCPUCapInfo;
5231 ULONG ulReserved3;
5239 ULONG ulReserved[19];
5241 ULONG ulGMCRestoreResetTime;
5242 ULONG ulReserved4;
5243 ULONG ulIdleNClk;
5244 ULONG ulDDR_DLL_PowerUpTime;
5245 ULONG ulDDR_PLL_PowerUpTime;
5254 ULONG ulGPUReservedSysMemBaseAddrLo;
5255 ULONG ulGPUReservedSysMemBaseAddrHi;
5256 ULONG ulReserved5[3];
5268 ULONG ulLCDBitDepthControlVal;
5269 ULONG ulNbpStateMemclkFreq[4];
5270 ULONG ulReserved6;
5271 ULONG ulNbpStateNClkFreq[4];
5428 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
5472 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5497 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5528 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6004 ULONG ulTargetMemoryClock; //In 10Khz unit
6042 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
6262 ULONG ulDllResetClkRange;
6268 ULONG ucMemBlkId:8;
6269 ULONG ulMemClockRange:24;
6271 ULONG ulMemClockRange:24;
6272 ULONG ucMemBlkId:8;
6279 ULONG ulAccess;
6285 ULONG aulMemData[];
6307 #define VALUE_DWORD SIZEOF ULONG
6324 ULONG ulARB_SEQDataBuf[32];
6375 ULONG ulSignature;
6393 ULONG ulReserved;
6415 ULONG ulReserved;
6416 ULONG ulFlags; // To enable/disable functionalities based on memory type
6417 ULONG ulEngineClock; // Override of default engine clock for particular memory type
6418 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
6443 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6479 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6512 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6548 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
6575 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
6597 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6639 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6670 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6702 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
6758 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6852 ULONG Ptr32_Bit;
6897 ULONG RsvdOffScrnMemSize;
6898 ULONG RsvdOffScrnMEmPtr;
6912 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6940 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6956 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
7250 ULONG ulReserved;
7257 ULONG ulReserved;
7327 ULONG ulAnalogSetting[];
7336 ULONG ulCondition;
7337 ULONG ulRegVal;
7341 ULONG ulCondition;
7343 ULONG ulRegVal;
7673 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7674 ULONG ulReserved1; // must set to 0
7675 ULONG ulReserved2; // must set to 0
7689 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7690 ULONG ulMiscInfo2;
7691 ULONG ulEngineClock;
7692 ULONG ulMemoryClock;
7704 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7705 ULONG ulMiscInfo2;
7706 ULONG ulEngineClock;
7707 ULONG ulMemoryClock;
7920 ULONG Signature;
7921 ULONG TableLength; //Length
7926 ULONG OemRevision;
7927 ULONG CreatorId;
7928 ULONG CreatorRevision;
7947 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
7948 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
7949 ULONG Reserved[4]; //0x3C
7953 ULONG PCIBus; //0x4C
7954 ULONG PCIDevice; //0x50
7955 ULONG PCIFunction; //0x54
7960 ULONG Revision; //0x60
7961 ULONG ImageLength; //0x64