omapdrm/dss/hdmi_wp.c

20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
46 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
51 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
53 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
58 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
63 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
67 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
70 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
74 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
77 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
87 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
90 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
93 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
102 int hdmi_wp_video_start(struct hdmi_wp_data *wp)
104 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
109 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
113 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
115 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
122 		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
130 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
135 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
140 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
143 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
153 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
160 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
163 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
178 	if (wp->version == 4)
184 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
189 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
225 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
232 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
233 	if (wp->version == 4) {
243 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
246 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
253 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
256 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
258 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
261 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
264 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
266 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
271 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
273 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
278 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
283 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
284 	wp->base = devm_ioremap_resource(&pdev->dev, res);
285 	if (IS_ERR(wp->base))
286 		return PTR_ERR(wp->base);
288 	wp->phys_base = res->start;
289 	wp->version = version;
294 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
296 	return wp->phys_base + HDMI_WP_AUDIO_DATA;