subdev/i2c/anx9805.c

33 	u8 addr;
39 	u8 addr;
53 	tmp = nvkm_rdi2cr(adap, pad->addr, 0x07) & ~0x10;
54 	nvkm_wri2cr(adap, pad->addr, 0x07, tmp | 0x10);
55 	nvkm_wri2cr(adap, pad->addr, 0x07, tmp);
56 	nvkm_wri2cr(adap, bus->addr, 0x43, 0x05);
60 		if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
61 			nvkm_wri2cr(adap, bus->addr, 0x40, msg->addr << 1);
62 			nvkm_wri2cr(adap, bus->addr, 0x41, seg);
63 			nvkm_wri2cr(adap, bus->addr, 0x42, off);
64 			nvkm_wri2cr(adap, bus->addr, 0x44, msg->len);
65 			nvkm_wri2cr(adap, bus->addr, 0x45, 0x00);
66 			nvkm_wri2cr(adap, bus->addr, 0x43, 0x01);
69 				while (nvkm_rdi2cr(adap, bus->addr, 0x46) & 0x10) {
74 				msg->buf[i] = nvkm_rdi2cr(adap, bus->addr, 0x47);
78 			if (msg->addr == 0x50 && msg->len == 0x01) {
81 			if (msg->addr == 0x30 && msg->len == 0x01) {
93 	nvkm_wri2cr(adap, bus->addr, 0x43, 0x00);
119 	switch (pad->addr) {
120 	case 0x39: bus->addr = 0x3d; break;
121 	case 0x3b: bus->addr = 0x3f; break;
132 	u8 addr;
137 		 u8 type, u32 addr, u8 *data, u8 *size)
146 	AUX_DBG(&aux->base, "%02x %05x %d", type, addr, *size);
148 	tmp = nvkm_rdi2cr(adap, pad->addr, 0x07) & ~0x04;
149 	nvkm_wri2cr(adap, pad->addr, 0x07, tmp | 0x04);
150 	nvkm_wri2cr(adap, pad->addr, 0x07, tmp);
151 	nvkm_wri2cr(adap, pad->addr, 0xf7, 0x01);
153 	nvkm_wri2cr(adap, aux->addr, 0xe4, 0x80);
158 			nvkm_wri2cr(adap, aux->addr, 0xf0 + i, buf[i]);
160 	nvkm_wri2cr(adap, aux->addr, 0xe5, ((*size - 1) << 4) | type);
161 	nvkm_wri2cr(adap, aux->addr, 0xe6, (addr & 0x000ff) >>  0);
162 	nvkm_wri2cr(adap, aux->addr, 0xe7, (addr & 0x0ff00) >>  8);
163 	nvkm_wri2cr(adap, aux->addr, 0xe8, (addr & 0xf0000) >> 16);
164 	nvkm_wri2cr(adap, aux->addr, 0xe9, 0x01);
167 	while ((tmp = nvkm_rdi2cr(adap, aux->addr, 0xe9)) & 0x01) {
173 	if ((tmp = nvkm_rdi2cr(adap, pad->addr, 0xf7)) & 0x01) {
180 			buf[i] = nvkm_rdi2cr(adap, aux->addr, 0xf0 + i);
187 	nvkm_wri2cr(adap, pad->addr, 0xf7, 0x01);
203 	nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw);
204 	nvkm_wri2cr(adap, aux->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
205 	nvkm_wri2cr(adap, aux->addr, 0xa2, 0x01);
206 	nvkm_wri2cr(adap, aux->addr, 0xa8, 0x01);
209 	while ((tmp = nvkm_rdi2cr(adap, aux->addr, 0xa8)) & 0x01) {
248 	switch (pad->addr) {
249 	case 0x39: aux->addr = 0x38; break;
250 	case 0x3b: aux->addr = 0x3c; break;
265 anx9805_pad_new(struct nvkm_i2c_bus *bus, int id, u8 addr,
276 	pad->addr = addr;