subdev/clk/nv50.c

32 read_div(struct nv50_clk *clk)
34 	struct nvkm_device *device = clk->base.subdev.device;
52 read_pll_src(struct nv50_clk *clk, u32 base)
54 	struct nvkm_subdev *subdev = &clk->base.subdev;
56 	u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);
103 		case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
104 		case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);
125 read_pll_ref(struct nv50_clk *clk, u32 base)
127 	struct nvkm_subdev *subdev = &clk->base.subdev;
145 		return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
152 		return nvkm_clk_read(&clk->base, nv_clk_src_href);
154 	return read_pll_src(clk, base);
158 read_pll(struct nv50_clk *clk, u32 base)
160 	struct nvkm_device *device = clk->base.subdev.device;
164 	u32 ref = read_pll_ref(clk, base);
171 			return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
194 	struct nv50_clk *clk = nv50_clk(base);
195 	struct nvkm_subdev *subdev = &clk->base.subdev;
206 		return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);
208 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
210 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;
213 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
216 		case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
223 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
224 		case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
225 		case 0x00000002: return read_pll(clk, 0x004020) >> P;
226 		case 0x00000003: return read_pll(clk, 0x004028) >> P;
234 				return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;
235 			return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
237 		case 0x00000020: return read_pll(clk, 0x004028) >> P;
238 		case 0x00000030: return read_pll(clk, 0x004020) >> P;
246 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
249 				return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;
252 			return read_pll(clk, 0x004008) >> P;
256 		P = (read_div(clk) & 0x00000700) >> 8;
267 					return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
268 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
273 					return read_pll(clk, 0x004028) >> P;
274 				return read_pll(clk, 0x004030) >> P;
276 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
282 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
286 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;
288 				return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;
297 			return read_pll(clk, 0x00e810) >> 2;
304 			P = (read_div(clk) & 0x00000007) >> 0;
306 			case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
308 			case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
310 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;
326 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
328 	struct nvkm_subdev *subdev = &clk->base.subdev;
337 	pll.refclk = read_pll_ref(clk, reg);
371 	struct nv50_clk *clk = nv50_clk(base);
372 	struct nv50_clk_hwsq *hwsq = &clk->hwsq;
373 	struct nvkm_subdev *subdev = &clk->base.subdev;
404 			out = read_pll(clk, 0x004030);
406 			out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);
427 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {
430 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {
433 			freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
460 	freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);
478 		freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
498 	struct nv50_clk *clk = nv50_clk(base);
499 	return clk_exec(&clk->hwsq, true);
505 	struct nv50_clk *clk = nv50_clk(base);
506 	clk_exec(&clk->hwsq, false);
513 	struct nv50_clk *clk;
516 	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
518 	ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);
519 	*pclk = &clk->base;
523 	clk->hwsq.r_fifo = hwsq_reg(0x002504);
524 	clk->hwsq.r_spll[0] = hwsq_reg(0x004020);
525 	clk->hwsq.r_spll[1] = hwsq_reg(0x004024);
526 	clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
527 	clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
532 		clk->hwsq.r_divs = hwsq_reg(0x004800);
535 		clk->hwsq.r_divs = hwsq_reg(0x004700);
538 	clk->hwsq.r_mast = hwsq_reg(0x00c040);