subdev/clk/base.c

42 		u8 pstate, u8 domain, u32 input)
49 	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate,
119 	if (!pstate || !cstate)
136 	list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
145 nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
149 		return list_last_entry(&pstate->list, typeof(*cstate), head);
151 		list_for_each_entry(cstate, &pstate->list, head) {
160 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
169 	if (!list_empty(&pstate->list)) {
170 		cstate = nvkm_cstate_get(clk, pstate, cstatei);
171 		cstate = nvkm_cstate_find_best(clk, pstate, cstate);
175 		cstate = &pstate->base;
179 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
188 				       pstate->base.voltage, clk->temp, +1);
203 				       pstate->base.voltage, clk->temp, -1);
209 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
225 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
246 	*cstate = pstate->base;
252 			u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
259 	list_add(&cstate->head, &pstate->list);
272 	struct nvkm_pstate *pstate;
275 	list_for_each_entry(pstate, &clk->states, head) {
281 	clk->pstate = pstatei;
283 	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);
287 		int khz = pstate->base.domain[nv_clk_src_mem];
296 	return nvkm_cstate_prog(clk, pstate, NVKM_CLK_CSTATE_HIGHEST);
304 	int pstate;
311 		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
314 	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
315 	if (clk->state_nr && pstate != -1) {
316 		pstate = (pstate < 0) ? clk->astate : pstate;
317 		pstate = min(pstate, clk->state_nr - 1);
318 		pstate = max(pstate, clk->dstate);
320 		pstate = clk->pstate = -1;
323 	nvkm_trace(subdev, "-> %d\n", pstate);
324 	if (pstate != clk->pstate) {
325 		int ret = nvkm_pstate_prog(clk, pstate);
327 			nvkm_error(subdev, "error setting pstate %d: %d\n",
328 				   pstate, ret);
346 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
355 	if (pstate->pstate != 0xff)
356 		snprintf(name, sizeof(name), "%02x", pstate->pstate);
359 		u32 lo = pstate->base.domain[clock->name];
365 		list_for_each_entry(cstate, &pstate->list, head) {
389 nvkm_pstate_del(struct nvkm_pstate *pstate)
393 	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
397 	list_del(&pstate->head);
398 	kfree(pstate);
406 	struct nvkm_pstate *pstate;
416 	if (perfE.pstate == 0xff)
419 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
420 	if (!pstate)
423 	INIT_LIST_HEAD(&pstate->list);
425 	pstate->pstate = perfE.pstate;
426 	pstate->fanspeed = perfE.fanspeed;
427 	pstate->pcie_speed = perfE.pcie_speed;
428 	pstate->pcie_width = perfE.pcie_width;
429 	cstate = &pstate->base;
447 							 pstate->pstate,
455 	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
459 			nvkm_cstate_new(clk, idx, pstate);
463 	nvkm_pstate_info(clk, pstate);
464 	list_add_tail(&pstate->head, &clk->states);
475 	struct nvkm_pstate *pstate;
482 		list_for_each_entry(pstate, &clk->states, head) {
483 			if (pstate->pstate == req)
488 		if (pstate->pstate != req)
598 	clk->bstate.pstate = 0xff;
617 	clk->pstate = -1;
627 	struct nvkm_pstate *pstate, *temp;
633 	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
634 		nvkm_pstate_del(pstate);