nvkm/nvfw/flcn.c

22 #include <core/subdev.h>
26 loader_config_dump(struct nvkm_subdev *subdev, const struct loader_config *hdr)
28 	nvkm_debug(subdev, "loaderConfig\n");
29 	nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
30 	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%xx\n", hdr->code_dma_base);
31 	nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
32 	nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
33 	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
34 	nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
35 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
36 	nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
37 	nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
38 	nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
39 	nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
40 	nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
41 	nvkm_debug(subdev, "\tovlyDmaBase1  : 0x%x\n", hdr->overlay_dma_base1);
45 loader_config_v1_dump(struct nvkm_subdev *subdev,
48 	nvkm_debug(subdev, "loaderConfig\n");
49 	nvkm_debug(subdev, "\treserved      : 0x%08x\n", hdr->reserved);
50 	nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
51 	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llxx\n", hdr->code_dma_base);
52 	nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
53 	nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
54 	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
55 	nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
56 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
57 	nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base);
58 	nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
59 	nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
63 flcn_bl_dmem_desc_dump(struct nvkm_subdev *subdev,
66 	nvkm_debug(subdev, "flcnBlDmemDesc\n");
67 	nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
70 	nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
73 	nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
74 	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%x\n", hdr->code_dma_base);
75 	nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
76 	nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
77 	nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
78 	nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
79 	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
80 	nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
81 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
82 	nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
83 	nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
87 flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *subdev,
90 	nvkm_debug(subdev, "flcnBlDmemDesc\n");
91 	nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
94 	nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
97 	nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
98 	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llx\n", hdr->code_dma_base);
99 	nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
100 	nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
101 	nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
102 	nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
103 	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
104 	nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
105 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
109 flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *subdev,
112 	flcn_bl_dmem_desc_v1_dump(subdev, (void *)hdr);
113 	nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
114 	nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);