Lines Matching refs:subdev
22 #include <core/subdev.h>
26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)
28 nvkm_debug(subdev, "wprHeader\n");
29 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
30 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
31 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
32 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
33 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);
37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)
39 nvkm_debug(subdev, "wprHeader\n");
40 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
41 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
42 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
43 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
44 nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version);
45 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);
49 wpr_generic_header_dump(struct nvkm_subdev *subdev, const struct wpr_generic_header *hdr)
51 nvkm_debug(subdev, "wprGenericHeader\n");
52 nvkm_debug(subdev, "\tidentifier : %04x\n", hdr->identifier);
53 nvkm_debug(subdev, "\tversion : %04x\n", hdr->version);
54 nvkm_debug(subdev, "\tsize : %08x\n", hdr->size);
58 wpr_header_v2_dump(struct nvkm_subdev *subdev, const struct wpr_header_v2 *hdr)
60 wpr_generic_header_dump(subdev, &hdr->hdr);
61 wpr_header_v1_dump(subdev, &hdr->wpr);
65 lsb_header_v2_dump(struct nvkm_subdev *subdev, struct lsb_header_v2 *hdr)
67 wpr_generic_header_dump(subdev, &hdr->hdr);
68 nvkm_debug(subdev, "lsbHeader\n");
69 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);
70 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);
71 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
72 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);
73 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);
74 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);
75 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);
76 nvkm_debug(subdev, "\treserved0 : %08x\n", hdr->rsvd0);
77 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);
78 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);
79 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);
80 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);
81 nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", hdr->app_imem_offset);
82 nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", hdr->app_dmem_offset);
83 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);
84 nvkm_debug(subdev, "\tmonitorCodeOff: 0x%x\n", hdr->monitor_code_offset);
85 nvkm_debug(subdev, "\tmonitorDataOff: 0x%x\n", hdr->monitor_data_offset);
86 nvkm_debug(subdev, "\tmanifestOffset: 0x%x\n", hdr->manifest_offset);
90 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr)
92 nvkm_debug(subdev, "lsbHeader\n");
93 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);
94 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);
95 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
96 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);
97 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);
98 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);
99 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);
100 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);
101 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);
102 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);
103 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);
104 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);
108 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)
110 lsb_header_tail_dump(subdev, &hdr->tail);
114 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)
116 lsb_header_tail_dump(subdev, &hdr->tail);
120 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)
124 nvkm_debug(subdev, "acrDesc\n");
125 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);
126 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);
127 nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n",
129 nvkm_debug(subdev, "\tnoRegions : %d\n",
133 nvkm_debug(subdev, "\tregion[%d] :\n", i);
134 nvkm_debug(subdev, "\t startAddr : 0x%x\n",
136 nvkm_debug(subdev, "\t endAddr : 0x%x\n",
138 nvkm_debug(subdev, "\t regionId : %d\n",
140 nvkm_debug(subdev, "\t readMask : 0x%x\n",
142 nvkm_debug(subdev, "\t writeMask : 0x%x\n",
144 nvkm_debug(subdev, "\t clientMask : 0x%x\n",
148 nvkm_debug(subdev, "\tucodeBlobSize: %d\n",
150 nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",
152 nvkm_debug(subdev, "\tvprEnabled : %d\n",
154 nvkm_debug(subdev, "\tvprStart : 0x%x\n",
156 nvkm_debug(subdev, "\tvprEnd : 0x%x\n",
158 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
163 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)
167 nvkm_debug(subdev, "acrDesc\n");
168 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);
169 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);
170 nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n",
172 nvkm_debug(subdev, "\tnoRegions : %d\n",
176 nvkm_debug(subdev, "\tregion[%d] :\n", i);
177 nvkm_debug(subdev, "\t startAddr : 0x%x\n",
179 nvkm_debug(subdev, "\t endAddr : 0x%x\n",
181 nvkm_debug(subdev, "\t regionId : %d\n",
183 nvkm_debug(subdev, "\t readMask : 0x%x\n",
185 nvkm_debug(subdev, "\t writeMask : 0x%x\n",
187 nvkm_debug(subdev, "\t clientMask : 0x%x\n",
189 nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n",
193 nvkm_debug(subdev, "\tucodeBlobSize : %d\n",
195 nvkm_debug(subdev, "\tucodeBlobBase : 0x%llx\n",
197 nvkm_debug(subdev, "\tvprEnabled : %d\n",
199 nvkm_debug(subdev, "\tvprStart : 0x%x\n",
201 nvkm_debug(subdev, "\tvprEnd : 0x%x\n",
203 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",