nvkm/nvfw/acr.c

26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)
29 	nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
30 	nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
31 	nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
32 	nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
33 	nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)
40 	nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
41 	nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
42 	nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
43 	nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
44 	nvkm_debug(subdev, "\tbinVersion    : %d\n", hdr->bin_version);
45 	nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
49 wpr_generic_header_dump(struct nvkm_subdev *subdev, const struct wpr_generic_header *hdr)
52 	nvkm_debug(subdev, "\tidentifier : %04x\n", hdr->identifier);
53 	nvkm_debug(subdev, "\tversion    : %04x\n", hdr->version);
54 	nvkm_debug(subdev, "\tsize       : %08x\n", hdr->size);
58 wpr_header_v2_dump(struct nvkm_subdev *subdev, const struct wpr_header_v2 *hdr)
60 	wpr_generic_header_dump(subdev, &hdr->hdr);
61 	wpr_header_v1_dump(subdev, &hdr->wpr);
65 lsb_header_v2_dump(struct nvkm_subdev *subdev, struct lsb_header_v2 *hdr)
67 	wpr_generic_header_dump(subdev, &hdr->hdr);
69 	nvkm_debug(subdev, "\tucodeOff      : 0x%x\n", hdr->ucode_off);
70 	nvkm_debug(subdev, "\tucodeSize     : 0x%x\n", hdr->ucode_size);
71 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
72 	nvkm_debug(subdev, "\tblCodeSize    : 0x%x\n", hdr->bl_code_size);
73 	nvkm_debug(subdev, "\tblImemOff     : 0x%x\n", hdr->bl_imem_off);
74 	nvkm_debug(subdev, "\tblDataOff     : 0x%x\n", hdr->bl_data_off);
75 	nvkm_debug(subdev, "\tblDataSize    : 0x%x\n", hdr->bl_data_size);
76 	nvkm_debug(subdev, "\treserved0     : %08x\n", hdr->rsvd0);
77 	nvkm_debug(subdev, "\tappCodeOff    : 0x%x\n", hdr->app_code_off);
78 	nvkm_debug(subdev, "\tappCodeSize   : 0x%x\n", hdr->app_code_size);
79 	nvkm_debug(subdev, "\tappDataOff    : 0x%x\n", hdr->app_data_off);
80 	nvkm_debug(subdev, "\tappDataSize   : 0x%x\n", hdr->app_data_size);
81 	nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", hdr->app_imem_offset);
82 	nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", hdr->app_dmem_offset);
83 	nvkm_debug(subdev, "\tflags         : 0x%x\n", hdr->flags);
84 	nvkm_debug(subdev, "\tmonitorCodeOff: 0x%x\n", hdr->monitor_code_offset);
85 	nvkm_debug(subdev, "\tmonitorDataOff: 0x%x\n", hdr->monitor_data_offset);
86 	nvkm_debug(subdev, "\tmanifestOffset: 0x%x\n", hdr->manifest_offset);
90 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr)
93 	nvkm_debug(subdev, "\tucodeOff      : 0x%x\n", hdr->ucode_off);
94 	nvkm_debug(subdev, "\tucodeSize     : 0x%x\n", hdr->ucode_size);
95 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
96 	nvkm_debug(subdev, "\tblCodeSize    : 0x%x\n", hdr->bl_code_size);
97 	nvkm_debug(subdev, "\tblImemOff     : 0x%x\n", hdr->bl_imem_off);
98 	nvkm_debug(subdev, "\tblDataOff     : 0x%x\n", hdr->bl_data_off);
99 	nvkm_debug(subdev, "\tblDataSize    : 0x%x\n", hdr->bl_data_size);
100 	nvkm_debug(subdev, "\tappCodeOff    : 0x%x\n", hdr->app_code_off);
101 	nvkm_debug(subdev, "\tappCodeSize   : 0x%x\n", hdr->app_code_size);
102 	nvkm_debug(subdev, "\tappDataOff    : 0x%x\n", hdr->app_data_off);
103 	nvkm_debug(subdev, "\tappDataSize   : 0x%x\n", hdr->app_data_size);
104 	nvkm_debug(subdev, "\tflags         : 0x%x\n", hdr->flags);
108 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)
110 	lsb_header_tail_dump(subdev, &hdr->tail);
114 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)
116 	lsb_header_tail_dump(subdev, &hdr->tail);
120 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)
125 	nvkm_debug(subdev, "\twprRegionId  : %d\n", hdr->wpr_region_id);
126 	nvkm_debug(subdev, "\twprOffset    : 0x%x\n", hdr->wpr_offset);
128 		   hdr->mmu_mem_range);
130 		   hdr->regions.no_regions);
132 	for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
135 			   hdr->regions.region_props[i].start_addr);
137 			   hdr->regions.region_props[i].end_addr);
139 			   hdr->regions.region_props[i].region_id);
141 			   hdr->regions.region_props[i].read_mask);
143 			   hdr->regions.region_props[i].write_mask);
145 			   hdr->regions.region_props[i].client_mask);
149 		   hdr->ucode_blob_size);
151 		   hdr->ucode_blob_base);
153 		   hdr->vpr_desc.vpr_enabled);
155 		   hdr->vpr_desc.vpr_start);
157 		   hdr->vpr_desc.vpr_end);
159 		   hdr->vpr_desc.hdcp_policies);
163 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)
168 	nvkm_debug(subdev, "\twprRegionId         : %d\n", hdr->wpr_region_id);
169 	nvkm_debug(subdev, "\twprOffset           : 0x%x\n", hdr->wpr_offset);
171 		   hdr->mmu_memory_range);
173 		   hdr->regions.no_regions);
175 	for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
178 			   hdr->regions.region_props[i].start_addr);
180 			   hdr->regions.region_props[i].end_addr);
182 			   hdr->regions.region_props[i].region_id);
184 			   hdr->regions.region_props[i].read_mask);
186 			   hdr->regions.region_props[i].write_mask);
188 			   hdr->regions.region_props[i].client_mask);
190 			   hdr->regions.region_props[i].shadow_mem_start_addr);
194 		   hdr->ucode_blob_size);
196 		   hdr->ucode_blob_base);
198 		   hdr->vpr_desc.vpr_enabled);
200 		   hdr->vpr_desc.vpr_start);
202 		   hdr->vpr_desc.vpr_end);
204 		   hdr->vpr_desc.hdcp_policies);