engine/gr/nv50.c

35 	return nvkm_rd32(gr->engine.subdev.device, 0x1540);
46 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
73 	int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
77 		nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
243 	struct nvkm_device *device = subdev->device;
244 	u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04);
245 	u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08);
246 	u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c);
247 	u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10);
248 	u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14);
249 	u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18);
250 	u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c);
285 	struct nvkm_device *device = subdev->device;
286 	u32 units = nvkm_rd32(device, 0x1540);
294 		if (device->chipset < 0xa0)
298 		mp10 = nvkm_rd32(device, addr + 0x10);
299 		status = nvkm_rd32(device, addr + 0x14);
303 			nvkm_rd32(device, addr + 0x20);
304 			pc = nvkm_rd32(device, addr + 0x24);
305 			oplow = nvkm_rd32(device, addr + 0x70);
306 			ophigh = nvkm_rd32(device, addr + 0x74);
315 		nvkm_wr32(device, addr + 0x10, mp10);
316 		nvkm_wr32(device, addr + 0x14, 0);
329 	struct nvkm_device *device = subdev->device;
330 	u32 units = nvkm_rd32(device, 0x1540);
338 		if (device->chipset < 0xa0)
342 		ustatus = nvkm_rd32(device, ustatus_addr) & 0x7fffffff;
352 						   nvkm_rd32(device, r));
387 		nvkm_wr32(device, ustatus_addr, 0xc0000000);
399 	struct nvkm_device *device = subdev->device;
400 	u32 status = nvkm_rd32(device, 0x400108);
413 		ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff;
418 		nvkm_wr32(device, 0x400500, 0x00000000);
422 			u32 addr = nvkm_rd32(device, 0x400808);
425 			u32 datal = nvkm_rd32(device, 0x40080c);
426 			u32 datah = nvkm_rd32(device, 0x400810);
427 			u32 class = nvkm_rd32(device, 0x400814);
428 			u32 r848 = nvkm_rd32(device, 0x400848);
443 			nvkm_wr32(device, 0x400808, 0);
444 			nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3);
445 			nvkm_wr32(device, 0x400848, 0);
450 			u32 addr = nvkm_rd32(device, 0x40084c);
453 			u32 data = nvkm_rd32(device, 0x40085c);
454 			u32 class = nvkm_rd32(device, 0x400814);
468 			nvkm_wr32(device, 0x40084c, 0);
477 		nvkm_wr32(device, 0x400804, 0xc0000000);
478 		nvkm_wr32(device, 0x400108, 0x001);
486 		u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff;
493 				   nvkm_rd32(device, 0x406804),
494 				   nvkm_rd32(device, 0x406808),
495 				   nvkm_rd32(device, 0x40680c),
496 				   nvkm_rd32(device, 0x406810));
500 		nvkm_wr32(device, 0x400040, 2);
501 		nvkm_wr32(device, 0x400040, 0);
502 		nvkm_wr32(device, 0x406800, 0xc0000000);
503 		nvkm_wr32(device, 0x400108, 0x002);
509 		u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff;
516 				   nvkm_rd32(device, 0x400c00),
517 				   nvkm_rd32(device, 0x400c08),
518 				   nvkm_rd32(device, 0x400c0c),
519 				   nvkm_rd32(device, 0x400c10));
522 		nvkm_wr32(device, 0x400c04, 0xc0000000);
523 		nvkm_wr32(device, 0x400108, 0x004);
529 		ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff;
536 				   nvkm_rd32(device, 0x401804),
537 				   nvkm_rd32(device, 0x401808),
538 				   nvkm_rd32(device, 0x40180c),
539 				   nvkm_rd32(device, 0x401810));
543 		nvkm_wr32(device, 0x400040, 0x80);
544 		nvkm_wr32(device, 0x400040, 0);
545 		nvkm_wr32(device, 0x401800, 0xc0000000);
546 		nvkm_wr32(device, 0x400108, 0x008);
552 		ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff;
560 				   nvkm_rd32(device, 0x405000),
561 				   nvkm_rd32(device, 0x405004),
562 				   nvkm_rd32(device, 0x405008),
563 				   nvkm_rd32(device, 0x40500c),
564 				   nvkm_rd32(device, 0x405010),
565 				   nvkm_rd32(device, 0x405014),
566 				   nvkm_rd32(device, 0x40501c));
569 		nvkm_wr32(device, 0x405018, 0xc0000000);
570 		nvkm_wr32(device, 0x400108, 0x010);
578 		ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff;
581 		nvkm_wr32(device, 0x402000, 0xc0000000);
589 		nvkm_wr32(device, 0x400108, 0x040);
597 		nvkm_wr32(device, 0x400108, 0x080);
606 		nvkm_wr32(device, 0x400108, 0x100);
613 		nvkm_wr32(device, 0x400108, status);
624 	struct nvkm_device *device = subdev->device;
626 	u32 stat = nvkm_rd32(device, 0x400100);
627 	u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff;
628 	u32 addr = nvkm_rd32(device, 0x400704);
631 	u32 data = nvkm_rd32(device, 0x400708);
632 	u32 class = nvkm_rd32(device, 0x400814);
647 		u32 ecode = nvkm_rd32(device, 0x400110);
660 	nvkm_wr32(device, 0x400100, stat);
661 	nvkm_wr32(device, 0x400500, 0x00010001);
672 	if (nvkm_rd32(device, 0x400824) & (1 << 31))
673 		nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31));
682 	struct nvkm_device *device = gr->base.engine.subdev.device;
686 	nvkm_wr32(device, 0x40008c, 0x00000004);
689 	nvkm_wr32(device, 0x400804, 0xc0000000);
690 	nvkm_wr32(device, 0x406800, 0xc0000000);
691 	nvkm_wr32(device, 0x400c04, 0xc0000000);
692 	nvkm_wr32(device, 0x401800, 0xc0000000);
693 	nvkm_wr32(device, 0x405018, 0xc0000000);
694 	nvkm_wr32(device, 0x402000, 0xc0000000);
696 	units = nvkm_rd32(device, 0x001540);
701 		if (device->chipset < 0xa0) {
702 			nvkm_wr32(device, 0x408900 + (i << 12), 0xc0000000);
703 			nvkm_wr32(device, 0x408e08 + (i << 12), 0xc0000000);
704 			nvkm_wr32(device, 0x408314 + (i << 12), 0xc0000000);
706 			nvkm_wr32(device, 0x408600 + (i << 11), 0xc0000000);
707 			nvkm_wr32(device, 0x408708 + (i << 11), 0xc0000000);
708 			nvkm_wr32(device, 0x40831c + (i << 11), 0xc0000000);
712 	nvkm_wr32(device, 0x400108, 0xffffffff);
713 	nvkm_wr32(device, 0x400138, 0xffffffff);
714 	nvkm_wr32(device, 0x400100, 0xffffffff);
715 	nvkm_wr32(device, 0x40013c, 0xffffffff);
716 	nvkm_wr32(device, 0x400500, 0x00010001);
719 	ret = nv50_grctx_init(device, &gr->size);
723 	nvkm_wr32(device, 0x400824, 0x00000000);
724 	nvkm_wr32(device, 0x400828, 0x00000000);
725 	nvkm_wr32(device, 0x40082c, 0x00000000);
726 	nvkm_wr32(device, 0x400830, 0x00000000);
727 	nvkm_wr32(device, 0x40032c, 0x00000000);
728 	nvkm_wr32(device, 0x400330, 0x00000000);
731 	switch (device->chipset & 0xf0) {
735 		nvkm_wr32(device, 0x402ca8, 0x00000800);
739 		if (device->chipset == 0xa0 ||
740 		    device->chipset == 0xaa ||
741 		    device->chipset == 0xac) {
742 			nvkm_wr32(device, 0x402ca8, 0x00000802);
744 			nvkm_wr32(device, 0x402cc0, 0x00000000);
745 			nvkm_wr32(device, 0x402ca8, 0x00000002);
753 		nvkm_wr32(device, 0x402c20 + (i * 0x10), 0x00000000);
754 		nvkm_wr32(device, 0x402c24 + (i * 0x10), 0x00000000);
755 		nvkm_wr32(device, 0x402c28 + (i * 0x10), 0x00000000);
756 		nvkm_wr32(device, 0x402c2c + (i * 0x10), 0x00000000);
763 nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
773 	return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
793 nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
795 	return nv50_gr_new_(&nv50_gr, device, type, inst, pgr);