engine/gr/nv10.c

401 	struct nv10_gr *gr;
414 #define PIPE_SAVE(gr, state, addr)					\
422 #define PIPE_RESTORE(gr, state, addr)					\
434 	struct nvkm_gr *gr = &chan->gr->base;
445 	nv04_gr_idle(gr);
452 	nv04_gr_idle(gr);
462 	nv04_gr_idle(gr);
485 	nv04_gr_idle(gr);
500 	nv04_gr_idle(gr);
507 	struct nvkm_gr *gr = &chan->gr->base;
509 	nv04_gr_idle(gr);
547 nv10_gr_channel(struct nv10_gr *gr)
549 	struct nvkm_device *device = gr->base.engine.subdev.device;
553 		if (chid < ARRAY_SIZE(gr->chan))
554 			chan = gr->chan[chid];
562 	struct nv10_gr *gr = chan->gr;
564 	struct nvkm_device *device = gr->base.engine.subdev.device;
566 	PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400);
567 	PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200);
568 	PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400);
569 	PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800);
570 	PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00);
571 	PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000);
572 	PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400);
573 	PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800);
574 	PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040);
575 	PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000);
581 	struct nv10_gr *gr = chan->gr;
583 	struct nvkm_device *device = gr->base.engine.subdev.device;
587 	nv04_gr_idle(&gr->base);
611 	PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200);
612 	nv04_gr_idle(&gr->base);
617 	PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400);
618 	PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800);
619 	PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00);
620 	PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000);
621 	PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400);
622 	PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800);
623 	PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400);
624 	PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000);
625 	PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040);
626 	nv04_gr_idle(&gr->base);
632 	struct nv10_gr *gr = chan->gr;
633 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
786 nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
788 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
799 nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
801 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
814 	struct nv10_gr *gr = chan->gr;
815 	struct nvkm_device *device = gr->base.engine.subdev.device;
885 	struct nv10_gr *gr = chan->gr;
886 	struct nvkm_device *device = gr->base.engine.subdev.device;
912 	struct nv10_gr *gr = chan->gr;
913 	struct nvkm_device *device = gr->base.engine.subdev.device;
932 nv10_gr_context_switch(struct nv10_gr *gr)
934 	struct nvkm_device *device = gr->base.engine.subdev.device;
939 	nv04_gr_idle(&gr->base);
942 	prev = nv10_gr_channel(gr);
948 	next = gr->chan[chid];
957 	struct nv10_gr *gr = chan->gr;
958 	struct nvkm_device *device = gr->base.engine.subdev.device;
961 	spin_lock_irqsave(&gr->lock, flags);
963 	if (nv10_gr_channel(gr) == chan)
966 	spin_unlock_irqrestore(&gr->lock, flags);
974 	struct nv10_gr *gr = chan->gr;
977 	spin_lock_irqsave(&gr->lock, flags);
978 	gr->chan[chan->chid] = NULL;
979 	spin_unlock_irqrestore(&gr->lock, flags);
990 	int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \
996 	int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \
1005 	struct nv10_gr *gr = nv10_gr(base);
1007 	struct nvkm_device *device = gr->base.engine.subdev.device;
1013 	chan->gr = gr;
1038 	spin_lock_irqsave(&gr->lock, flags);
1039 	gr->chan[chan->chid] = chan;
1040 	spin_unlock_irqrestore(&gr->lock, flags);
1051 	struct nv10_gr *gr = nv10_gr(base);
1052 	struct nvkm_device *device = gr->base.engine.subdev.device;
1057 	nv04_gr_idle(&gr->base);
1083 	struct nv10_gr *gr = nv10_gr(base);
1084 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1100 	spin_lock_irqsave(&gr->lock, flags);
1101 	chan = gr->chan[chid];
1114 		nv10_gr_context_switch(gr);
1132 	spin_unlock_irqrestore(&gr->lock, flags);
1138 	struct nv10_gr *gr = nv10_gr(base);
1139 	struct nvkm_device *device = gr->base.engine.subdev.device;
1178 	struct nv10_gr *gr;
1180 	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
1182 	spin_lock_init(&gr->lock);
1183 	*pgr = &gr->base;
1185 	return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);