engine/gr/gv100.c

28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm)
30 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
51 	gv100_gr_trap_sm(gr, gpc, tpc, 0);
52 	gv100_gr_trap_sm(gr, gpc, tpc, 1);
56 gv100_gr_init_4188a4(struct gf100_gr *gr)
58 	struct nvkm_device *device = gr->base.engine.subdev.device;
64 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
66 	struct nvkm_device *device = gr->base.engine.subdev.device;
75 gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
77 	struct nvkm_device *device = gr->base.engine.subdev.device;
82 gv100_gr_init_419bd8(struct gf100_gr *gr)
84 	struct nvkm_device *device = gr->base.engine.subdev.device;
89 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc)
93 	for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
94 		if (gr->ppc_tpc_mask[gpc][pes] & BIT(tpc))
97 		tpc_new += gr->ppc_tpc_nr[gpc][pes];
100 	temp = (BIT(tpc) - 1) & gr->ppc_tpc_mask[gpc][pes];
106 gv100_gr_scg_estimate_perf(struct gf100_gr *gr, unsigned long *gpc_tpc_mask,
131 	if (!(num_tpc_gpc = kcalloc(gr->gpc_nr, sizeof(*num_tpc_gpc), GFP_KERNEL)))
135 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
160 		scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc] / gr->tpc_nr[gpc];
165 		for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
167 			num_tpc_mask = gr->ppc_tpc_mask[gpc][pes] & gpc_tpc_mask[gpc];
191 	scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_total;
193 	average_tpcs = scale_factor * average_tpcs / gr->gpc_nr;
194 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
202 	deviation /= gr->gpc_nr;
227 gv100_gr_oneinit_sm_id(struct gf100_gr *gr)
234 	gpc_tpc_mask = kcalloc(gr->gpc_nr, sizeof(*gpc_tpc_mask), GFP_KERNEL);
235 	gpc_table = kcalloc(gr->tpc_total, sizeof(*gpc_table), GFP_KERNEL);
236 	tpc_table = kcalloc(gr->tpc_total, sizeof(*tpc_table), GFP_KERNEL);
242 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
243 		for (pes = 0; pes < gr->ppc_nr[gpc]; pes++)
244 			gpc_tpc_mask[gpc] |= gr->ppc_tpc_mask[gpc][pes];
247 	for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
248 		for (maxperf = -1, gpc = 0; gpc < gr->gpc_nr; gpc++) {
249 			for_each_set_bit(tpc, &gpc_tpc_mask[gpc], gr->tpc_nr[gpc]) {
250 				ret = gv100_gr_scg_estimate_perf(gr, gpc_tpc_mask, gpc, tpc, &perf);
267 	for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
268 		gr->sm[gtpc].gpc = gpc_table[gtpc];
269 		gr->sm[gtpc].tpc = tpc_table[gtpc];
270 		gr->sm_nr++;
318 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin");
319 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin");
320 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin");
321 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin");
322 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin");
323 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin");
324 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin");
325 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin");
326 MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin");
327 MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin");
328 MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin");
329 MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin");