Lines Matching defs:gr
30 gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc)
32 struct nvkm_device *device = gr->base.engine.subdev.device;
36 if (gr->zbc_stencil[zbc].format)
37 nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds);
40 gr->zbc_stencil[zbc].format << ((znum % 4) * 7));
44 gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format,
47 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
51 if (gr->zbc_stencil[i].format) {
52 if (gr->zbc_stencil[i].format != format)
54 if (gr->zbc_stencil[i].ds != ds)
56 if (gr->zbc_stencil[i].l2 != l2) {
69 gr->zbc_stencil[zbc].format = format;
70 gr->zbc_stencil[zbc].ds = ds;
71 gr->zbc_stencil[zbc].l2 = l2;
73 gr->func->zbc->clear_stencil(gr, zbc);
86 gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr)
88 struct nvkm_device *device = gr->base.engine.subdev.device;
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
137 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
138 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
139 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
140 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
141 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
142 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
143 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
144 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
145 MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
146 MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
147 MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
148 MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");