engine/gr/gp100.c

33 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
35 	struct nvkm_device *device = gr->base.engine.subdev.device;
39 	if (gr->zbc_color[zbc].format) {
40 		nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);
41 		nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);
42 		nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);
43 		nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);
48 			  gr->zbc_color[zbc].format << ((znum % 4) * 7));
52 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
54 	struct nvkm_device *device = gr->base.engine.subdev.device;
58 	if (gr->zbc_depth[zbc].format)
59 		nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);
62 			  gr->zbc_depth[zbc].format << ((znum % 4) * 7));
72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
74 	struct nvkm_device *device = gr->base.engine.subdev.device;
80 gp100_gr_init_419c9c(struct gf100_gr *gr)
82 	struct nvkm_device *device = gr->base.engine.subdev.device;
88 gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
90 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000e0002);
94 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
96 	struct nvkm_device *device = gr->base.engine.subdev.device;
141 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin");
142 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin");
143 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin");
144 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin");
145 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin");
146 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin");
147 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin");
148 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin");
149 MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin");
150 MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin");
151 MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin");
152 MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin");