engine/gr/gm200.c

35 gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
37 	nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n");
92 gm200_gr_rops(struct gf100_gr *gr)
94 	return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
98 gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)
100 	struct nvkm_device *device = gr->base.engine.subdev.device;
106 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)
108 	struct nvkm_device *device = gr->base.engine.subdev.device;
114 gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
116 	struct nvkm_device *device = gr->base.engine.subdev.device;
128 gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
130 	struct nvkm_device *device = gr->base.engine.subdev.device;
152 gm200_gr_oneinit_sm_id(struct gf100_gr *gr)
155 	return gf100_gr_oneinit_sm_id(gr);
159 gm200_gr_oneinit_tiles(struct gf100_gr *gr)
167 	if (gr->gpc_nr == 2 && gr->tpc_total == 8) {
168 		memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
169 		gr->screen_tile_row_offset = 1;
171 	if (gr->gpc_nr == 4 && gr->tpc_total == 16) {
172 		memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
173 		gr->screen_tile_row_offset = 4;
175 	if (gr->gpc_nr == 6 && gr->tpc_total == 24) {
176 		memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);
177 		gr->screen_tile_row_offset = 5;
179 		gf100_gr_oneinit_tiles(gr);
222 gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
226 	ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
227 						  &gr->fecs.falcon,
229 						  "gr/fecs_", ver, fwif->fecs);
233 	ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
234 						  &gr->gpccs.falcon,
236 						  "gr/gpccs_", ver,
241 	gr->firmware = true;
243 	return gk20a_gr_load_sw(gr, "gr/", ver);
246 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
247 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
248 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
249 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
250 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
251 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
252 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
253 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
254 MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
255 MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
256 MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
257 MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
259 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
260 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
261 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
262 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
263 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
264 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
265 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
266 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
267 MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
268 MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
269 MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
270 MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
272 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
273 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
274 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
275 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
276 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
277 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
278 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
279 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
280 MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
281 MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
282 MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
283 MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");