Lines Matching defs:device
51 struct nvkm_device *device = gr->base.engine.subdev.device;
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
59 nvkm_wr32(device, 0x405820, zbc);
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
102 struct nvkm_device *device = gr->base.engine.subdev.device;
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
106 nvkm_wr32(device, 0x405820, zbc);
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
265 gf100_gr_mthd_set_shader_exceptions(device, data);
327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
384 struct nvkm_device *device = gr->base.engine.subdev.device;
417 if (device->card_type < GP100) {
455 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
746 return nvkm_rd32(gr->engine.subdev.device, 0x409b00);
752 struct nvkm_device *device = gr->base.engine.subdev.device;
754 nvkm_wr32(device, 0x409804, 0xffffffff);
755 nvkm_wr32(device, 0x409800, 0x00000000);
756 nvkm_wr32(device, 0x409500, 0xffffffff);
757 nvkm_wr32(device, 0x409504, mthd);
758 nvkm_msec(device, 2000,
759 u32 stat = nvkm_rd32(device, 0x409804);
816 struct nvkm_device *device = gr->base.engine.subdev.device;
818 nvkm_mask(device, 0x409800, 0x00000003, 0x00000000);
819 nvkm_wr32(device, 0x409500, inst);
820 nvkm_wr32(device, 0x409504, 0x00000009);
821 nvkm_msec(device, 2000,
822 u32 stat = nvkm_rd32(device, 0x409800);
835 struct nvkm_device *device = gr->base.engine.subdev.device;
837 nvkm_mask(device, 0x409800, 0x00000030, 0x00000000);
838 nvkm_wr32(device, 0x409500, inst);
839 nvkm_wr32(device, 0x409504, 0x00000003);
840 nvkm_msec(device, 2000,
841 u32 stat = nvkm_rd32(device, 0x409800);
854 struct nvkm_device *device = gr->base.engine.subdev.device;
856 nvkm_wr32(device, 0x409810, addr >> 8);
857 nvkm_wr32(device, 0x409800, 0x00000000);
858 nvkm_wr32(device, 0x409500, 0x00000001);
859 nvkm_wr32(device, 0x409504, 0x00000032);
860 nvkm_msec(device, 2000,
861 if (nvkm_rd32(device, 0x409800) == 0x00000001)
871 struct nvkm_device *device = gr->base.engine.subdev.device;
873 nvkm_wr32(device, 0x409810, inst);
874 nvkm_wr32(device, 0x409800, 0x00000000);
875 nvkm_wr32(device, 0x409500, 0x00000001);
876 nvkm_wr32(device, 0x409504, 0x00000031);
877 nvkm_msec(device, 2000,
878 if (nvkm_rd32(device, 0x409800) == 0x00000001)
888 struct nvkm_device *device = gr->base.engine.subdev.device;
890 nvkm_wr32(device, 0x409800, 0x00000000);
891 nvkm_wr32(device, 0x409500, 0x00000001);
892 nvkm_wr32(device, 0x409504, 0x00000030);
893 nvkm_msec(device, 2000,
894 if ((*psize = nvkm_rd32(device, 0x409800)))
926 struct nvkm_device *device = gr->base.engine.subdev.device;
928 nvkm_wr32(device, 0x409800, 0x00000000);
929 nvkm_wr32(device, 0x409500, 0x00000000);
930 nvkm_wr32(device, 0x409504, 0x00000025);
931 nvkm_msec(device, 2000,
932 if ((*psize = nvkm_rd32(device, 0x409800)))
942 struct nvkm_device *device = gr->base.engine.subdev.device;
944 nvkm_wr32(device, 0x409800, 0x00000000);
945 nvkm_wr32(device, 0x409500, 0x00000000);
946 nvkm_wr32(device, 0x409504, 0x00000016);
947 nvkm_msec(device, 2000,
948 if ((*psize = nvkm_rd32(device, 0x409800)))
958 struct nvkm_device *device = gr->base.engine.subdev.device;
960 nvkm_wr32(device, 0x409800, 0x00000000);
961 nvkm_wr32(device, 0x409500, 0x00000000);
962 nvkm_wr32(device, 0x409504, 0x00000010);
963 nvkm_msec(device, 2000,
964 if ((*psize = nvkm_rd32(device, 0x409800)))
974 struct nvkm_device *device = gr->base.engine.subdev.device;
976 nvkm_wr32(device, 0x409800, 0x00000000);
977 nvkm_wr32(device, 0x409500, timeout);
978 nvkm_wr32(device, 0x409504, 0x00000021);
986 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
990 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
1000 struct nvkm_device *device = gr->base.engine.subdev.device;
1001 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
1015 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
1052 struct nvkm_device *device = subdev->device;
1061 nvkm_rd32(device, 0x400700);
1063 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
1065 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
1080 struct nvkm_device *device = gr->base.engine.subdev.device;
1088 nvkm_wr32(device, addr, init->data);
1097 struct nvkm_device *device = gr->base.engine.subdev.device;
1102 nvkm_wr32(device, 0x400208, 0x80000000);
1109 nvkm_wr32(device, 0x400204, init->data);
1111 nvkm_wr32(device, 0x40020c, upper_32_bits(init->data));
1116 nvkm_wr32(device, 0x400200, addr);
1123 nvkm_msec(device, 2000,
1124 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
1131 nvkm_wr32(device, 0x400208, 0x00000000);
1137 struct nvkm_device *device = gr->base.engine.subdev.device;
1148 nvkm_wr32(device, 0x40448c, init->data);
1153 nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
1237 struct nvkm_device *device = subdev->device;
1241 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
1242 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
1243 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
1244 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
1252 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1298 struct nvkm_device *device = subdev->device;
1299 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1300 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
1311 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1312 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
1319 struct nvkm_device *device = subdev->device;
1320 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
1323 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
1325 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
1335 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
1337 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
1342 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
1344 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
1349 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1351 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1364 struct nvkm_device *device = subdev->device;
1365 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
1374 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
1376 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1381 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
1383 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1388 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
1390 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1398 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
1412 struct nvkm_device *device = subdev->device;
1414 u32 trap = nvkm_rd32(device, 0x400108);
1418 u32 stat = nvkm_rd32(device, 0x404000);
1423 nvkm_wr32(device, 0x404000, 0xc0000000);
1424 nvkm_wr32(device, 0x400108, 0x00000001);
1429 u32 stat = nvkm_rd32(device, 0x404600);
1435 nvkm_wr32(device, 0x404600, 0xc0000000);
1436 nvkm_wr32(device, 0x400108, 0x00000002);
1441 u32 stat = nvkm_rd32(device, 0x408030);
1446 nvkm_wr32(device, 0x408030, 0xc0000000);
1447 nvkm_wr32(device, 0x400108, 0x00000008);
1452 u32 stat = nvkm_rd32(device, 0x405840);
1455 nvkm_wr32(device, 0x405840, 0xc0000000);
1456 nvkm_wr32(device, 0x400108, 0x00000010);
1461 u32 stat = nvkm_rd32(device, 0x40601c);
1467 nvkm_wr32(device, 0x40601c, 0xc0000000);
1468 nvkm_wr32(device, 0x400108, 0x00000040);
1473 u32 stat = nvkm_rd32(device, 0x404490);
1474 u32 pc = nvkm_rd32(device, 0x404494);
1475 u32 op = nvkm_rd32(device, 0x40449c);
1484 nvkm_wr32(device, 0x404490, 0xc0000000);
1485 nvkm_wr32(device, 0x400108, 0x00000080);
1490 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
1496 nvkm_wr32(device, 0x407020, 0x40000000);
1497 nvkm_wr32(device, 0x400108, 0x00000100);
1502 u32 stat = nvkm_rd32(device, 0x400118);
1507 nvkm_wr32(device, 0x400118, mask);
1511 nvkm_wr32(device, 0x400108, 0x01000000);
1517 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1518 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1521 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1522 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1524 nvkm_wr32(device, 0x400108, 0x02000000);
1530 nvkm_wr32(device, 0x400108, trap);
1538 struct nvkm_device *device = subdev->device;
1540 nvkm_rd32(device, base + 0x400));
1542 nvkm_rd32(device, base + 0x800),
1543 nvkm_rd32(device, base + 0x804),
1544 nvkm_rd32(device, base + 0x808),
1545 nvkm_rd32(device, base + 0x80c));
1547 nvkm_rd32(device, base + 0x810),
1548 nvkm_rd32(device, base + 0x814),
1549 nvkm_rd32(device, base + 0x818),
1550 nvkm_rd32(device, base + 0x81c));
1556 struct nvkm_device *device = gr->base.engine.subdev.device;
1557 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1569 struct nvkm_device *device = subdev->device;
1570 u32 stat = nvkm_rd32(device, 0x409c18);
1573 u32 code = nvkm_rd32(device, 0x409814);
1575 u32 class = nvkm_rd32(device, 0x409808);
1576 u32 addr = nvkm_rd32(device, 0x40980c);
1579 u32 data = nvkm_rd32(device, 0x409810);
1587 nvkm_wr32(device, 0x409c20, 0x00000001);
1594 nvkm_wr32(device, 0x409c20, 0x00080000);
1601 nvkm_wr32(device, 0x409c20, stat);
1610 struct nvkm_device *device = subdev->device;
1613 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1614 u32 stat = nvkm_rd32(device, 0x400100);
1615 u32 addr = nvkm_rd32(device, 0x400704);
1618 u32 data = nvkm_rd32(device, 0x400708);
1619 u32 code = nvkm_rd32(device, 0x400110);
1630 if (device->card_type < NV_E0 || subc < 4)
1631 class = nvkm_rd32(device, 0x404200 + (subc * 4));
1640 nvkm_wr32(device, 0x400100, 0x00000001);
1645 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
1651 nvkm_wr32(device, 0x400100, 0x00000010);
1659 nvkm_wr32(device, 0x400100, 0x00000020);
1670 nvkm_wr32(device, 0x400100, 0x00100000);
1678 nvkm_wr32(device, 0x400100, 0x00200000);
1684 nvkm_wr32(device, 0x400100, 0x00080000);
1690 nvkm_wr32(device, 0x400100, stat);
1693 nvkm_wr32(device, 0x400500, 0x00010001);
1711 struct nvkm_device *device = gr->base.engine.subdev.device;
1717 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1718 star = nvkm_rd32(device, falcon + 0x01c4);
1719 temp = nvkm_rd32(device, falcon + 0x01c4);
1722 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1731 nvkm_wr32(device, falcon + 0x01c4, data);
1743 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1744 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1745 nvkm_wr32(device, falcon + 0x01c4, star + 4);
1753 struct nvkm_device *device = subdev->device;
1758 nvkm_mc_unk260(device, 0);
1762 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) {
1769 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) {
1777 ret = nvkm_acr_bootstrap_falcons(device, lsf_mask);
1782 nvkm_mc_unk260(device, 1);
1785 nvkm_wr32(device, 0x409800, 0x00000000);
1786 nvkm_wr32(device, 0x41a10c, 0x00000000);
1787 nvkm_wr32(device, 0x40910c, 0x00000000);
1792 if (nvkm_msec(device, 2000,
1793 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1835 struct nvkm_device *device = subdev->device;
1842 nvkm_mc_unk260(device, 0);
1857 nvkm_mc_unk260(device, 1);
1867 nvkm_wr32(device, 0x40910c, 0x00000000);
1868 nvkm_wr32(device, 0x409100, 0x00000002);
1869 if (nvkm_msec(device, 2000,
1870 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1877 gr->size = nvkm_rd32(device, 0x409804);
1993 struct nvkm_device *device = subdev->device;
1994 struct nvkm_intr *intr = &device->mc->intr;
2006 nvkm_pmu_pgob(device->pmu, false);
2009 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
2011 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
2016 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
2035 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST_SR_LOST,
2040 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST_SR_LOST, gr->func->grctx->bundle_size,
2045 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST_SR_LOST,
2051 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size,
2068 struct nvkm_device *device = subdev->device;
2069 bool reset = device->chipset == 0x137 || device->chipset == 0x138;
2087 reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset);
2089 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
2090 nvkm_rd32(device, 0x000200);
2092 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
2093 nvkm_rd32(device, 0x000200);
2096 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
2171 struct nvkm_device *device = gr->base.engine.subdev.device;
2179 nvkm_wr32(device, 0x406028 + (i * 4), data);
2181 nvkm_wr32(device, 0x405870 + (i * 4), data);
2188 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
2194 struct nvkm_device *device = gr->base.engine.subdev.device;
2196 nvkm_wr32(device, 0x40011c, 0xffffffff);
2197 nvkm_wr32(device, 0x400134, 0xffffffff);
2203 struct nvkm_device *device = gr->base.engine.subdev.device;
2207 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
2208 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
2209 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2210 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
2217 struct nvkm_device *device = gr->base.engine.subdev.device;
2218 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2219 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
2225 struct nvkm_device *device = gr->base.engine.subdev.device;
2226 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2232 struct nvkm_device *device = gr->base.engine.subdev.device;
2233 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
2239 struct nvkm_device *device = gr->base.engine.subdev.device;
2242 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
2246 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2253 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
2260 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
2266 struct nvkm_device *device = gr->base.engine.subdev.device;
2267 struct nvkm_fb *fb = device->fb;
2269 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
2270 nvkm_wr32(device, 0x4188a4, 0x03000000);
2271 nvkm_wr32(device, 0x418888, 0x00000000);
2272 nvkm_wr32(device, 0x41888c, 0x00000000);
2273 nvkm_wr32(device, 0x418890, 0x00000000);
2274 nvkm_wr32(device, 0x418894, 0x00000000);
2275 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
2276 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
2282 struct nvkm_device *device = gr->base.engine.subdev.device;
2283 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
2289 struct nvkm_device *device = gr->base.engine.subdev.device;
2300 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
2304 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
2306 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
2308 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
2311 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
2317 struct nvkm_device *device = gr->base.engine.subdev.device;
2318 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
2325 struct nvkm_device *device = subdev->device;
2328 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000);
2333 nvkm_mc_disable(device, subdev->type, subdev->inst);
2337 nvkm_mc_enable(device, subdev->type, subdev->inst);
2344 struct nvkm_device *device = gr->base.engine.subdev.device;
2347 nvkm_mask(device, 0x400500, 0x00010001, 0x00000000);
2369 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack);
2386 nvkm_wr32(device, 0x400500, 0x00010001);
2388 nvkm_wr32(device, 0x400100, 0xffffffff);
2389 nvkm_wr32(device, 0x40013c, 0xffffffff);
2390 nvkm_wr32(device, 0x400124, 0x00000002);
2400 nvkm_wr32(device, 0x404000, 0xc0000000);
2401 nvkm_wr32(device, 0x404600, 0xc0000000);
2402 nvkm_wr32(device, 0x408030, 0xc0000000);
2407 nvkm_wr32(device, 0x406018, 0xc0000000);
2408 nvkm_wr32(device, 0x404490, 0xc0000000);
2413 nvkm_wr32(device, 0x405840, 0xc0000000);
2414 nvkm_wr32(device, 0x405844, 0x00ffffff);
2427 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
2428 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
2429 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
2430 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
2432 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2433 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2436 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2441 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2442 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
2447 nvkm_wr32(device, 0x400108, 0xffffffff);
2448 nvkm_wr32(device, 0x400138, 0xffffffff);
2449 nvkm_wr32(device, 0x400118, 0xffffffff);
2450 nvkm_wr32(device, 0x400130, 0xffffffff);
2468 struct nvkm_device *device = gr->base.engine.subdev.device;
2470 nvkm_wr32(device, 0x409614, 0x00000070);
2471 nvkm_usec(device, 10, NVKM_DELAY);
2472 nvkm_mask(device, 0x409614, 0x00000700, 0x00000700);
2473 nvkm_usec(device, 10, NVKM_DELAY);
2474 nvkm_rd32(device, 0x409614);
2572 struct nvkm_device *device = subdev->device;
2577 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name);
2578 ret = request_firmware(&fw, f, device->dev);
2581 ret = request_firmware(&fw, f, device->dev);
2597 struct nvkm_device *device = gr->base.engine.subdev.device;
2599 if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false))
2620 gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device,
2630 ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base);
2656 gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
2658 return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr);