engine/gr/ga102.c

36 ga102_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
38 	struct nvkm_device *device = gr->base.engine.subdev.device;
41 	if (gr->zbc_color[zbc].format)
42 		color = gr->zbc_color[zbc].l2;
62 ga102_gr_gpccs_reset(struct gf100_gr *gr)
64 	struct nvkm_device *device = gr->base.engine.subdev.device;
81 ga102_gr_fecs_reset(struct gf100_gr *gr)
83 	struct nvkm_device *device = gr->base.engine.subdev.device;
104 ga102_gr_init_rop_exceptions(struct gf100_gr *gr)
106 	struct nvkm_device *device = gr->base.engine.subdev.device;
114 ga102_gr_init_40a790(struct gf100_gr *gr)
116 	nvkm_wr32(gr->base.engine.subdev.device, 0x40a790, 0xc0000000);
120 ga102_gr_init_gpc_mmu(struct gf100_gr *gr)
122 	struct nvkm_device *device = gr->base.engine.subdev.device;
133 ga102_gr_oneinit_intr(struct gf100_gr *gr, enum nvkm_intr_type *pvector)
135 	struct nvkm_device *device = gr->base.engine.subdev.device;
142 ga102_gr_nonstall(struct gf100_gr *gr)
144 	return nvkm_rd32(gr->base.engine.subdev.device, 0x400160) & 0x00000fff;
188 MODULE_FIRMWARE("nvidia/ga102/gr/fecs_bl.bin");
189 MODULE_FIRMWARE("nvidia/ga102/gr/fecs_sig.bin");
190 MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_bl.bin");
191 MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_sig.bin");
192 MODULE_FIRMWARE("nvidia/ga102/gr/NET_img.bin");
194 MODULE_FIRMWARE("nvidia/ga103/gr/fecs_bl.bin");
195 MODULE_FIRMWARE("nvidia/ga103/gr/fecs_sig.bin");
196 MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_bl.bin");
197 MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_sig.bin");
198 MODULE_FIRMWARE("nvidia/ga103/gr/NET_img.bin");
200 MODULE_FIRMWARE("nvidia/ga104/gr/fecs_bl.bin");
201 MODULE_FIRMWARE("nvidia/ga104/gr/fecs_sig.bin");
202 MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_bl.bin");
203 MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_sig.bin");
204 MODULE_FIRMWARE("nvidia/ga104/gr/NET_img.bin");
206 MODULE_FIRMWARE("nvidia/ga106/gr/fecs_bl.bin");
207 MODULE_FIRMWARE("nvidia/ga106/gr/fecs_sig.bin");
208 MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_bl.bin");
209 MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_sig.bin");
210 MODULE_FIRMWARE("nvidia/ga106/gr/NET_img.bin");
212 MODULE_FIRMWARE("nvidia/ga107/gr/fecs_bl.bin");
213 MODULE_FIRMWARE("nvidia/ga107/gr/fecs_sig.bin");
214 MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_bl.bin");
215 MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_sig.bin");
216 MODULE_FIRMWARE("nvidia/ga107/gr/NET_img.bin");
272 ga102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
274 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
283 	ret = nvkm_firmware_get(subdev, "gr/NET_img", 0, &fw);
306 		case  4: gk20a_gr_av_to_init(&blob, &gr->bundle); break;
307 		case  5: gk20a_gr_aiv_to_init(&blob, &gr->sw_ctx); break;
308 		case  7: gk20a_gr_av_to_method(&blob, &gr->method); break;
309 		case 28: tu102_gr_av_to_init_veid(&blob, &gr->bundle_veid); break;
310 		case 34: ga102_gr_av64_to_init(&blob, &gr->bundle64); break;
311 		case 48: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx1); break;
312 		case 49: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx2); break;
313 		case 50: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx3); break;
314 		case 51: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx4); break;
320 	ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->fecs.falcon, NVKM_ACR_LSF_FECS,
321 					    "gr/fecs_", ver, fwif->fecs,
329 	ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->gpccs.falcon, NVKM_ACR_LSF_GPCCS,
330 					    "gr/gpccs_", ver, fwif->gpccs,
338 	gr->firmware = true;