engine/fifo/nv04.c

26 #include "chan.h"
41 nv04_chan_stop(struct nvkm_chan *chan)
43 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
48 	u32 data = chan->ramfc_offset;
57 	if (chid == chan->id) {
62 		c = chan->func->ramfc->layout;
73 		c = chan->func->ramfc->layout;
86 	nvkm_mask(device, NV04_PFIFO_MODE, BIT(chan->id), 0);
92 nv04_chan_start(struct nvkm_chan *chan)
94 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
98 	nvkm_mask(fifo->engine.subdev.device, NV04_PFIFO_MODE, BIT(chan->id), BIT(chan->id));
103 nv04_chan_ramfc_clear(struct nvkm_chan *chan)
105 	struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
106 	const struct nvkm_ramfc_layout *c = chan->func->ramfc->layout;
110 		nvkm_wo32(ramfc, chan->ramfc_offset + c->ctxp, 0x00000000);
116 nv04_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
118 	struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
119 	const u32 base = chan->id * 32;
121 	chan->ramfc_offset = base;
126 	nvkm_wo32(ramfc, base + 0x08, chan->push->addr >> 4);
181 nv04_eobj_ramht_del(struct nvkm_chan *chan, int hash)
183 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
192 nv04_eobj_ramht_add(struct nvkm_engn *engn, struct nvkm_object *eobj, struct nvkm_chan *chan)
194 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
196 	u32 context = 0x80000000 | chan->id << 24 | engn->id << 16;
200 	hash = nvkm_ramht_insert(imem->ramht, eobj, chan->id, 4, eobj->handle, context);
307 	struct nvkm_chan *chan;
330 		chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
333 			   chid, chan ? chan->name : "unknown",
335 		nvkm_chan_put(&chan, flags);
362 	struct nvkm_chan *chan;
366 	chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
367 	name = chan ? chan->name : "unknown";
398 	nvkm_chan_put(&chan, flags);
535 	.chan = {{ 0, 0, NV03_CHANNEL_DMA }, &nv04_chan },