engine/fifo/nv04.c

43 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
44 	struct nvkm_device *device = fifo->engine.subdev.device;
51 	/* prevent fifo context switches */
52 	spin_lock_irqsave(&fifo->lock, flags);
56 	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;
80 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
88 	spin_unlock_irqrestore(&fifo->lock, flags);
94 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
97 	spin_lock_irqsave(&fifo->lock, flags);
98 	nvkm_mask(fifo->engine.subdev.device, NV04_PFIFO_MODE, BIT(chan->id), BIT(chan->id));
99 	spin_unlock_irqrestore(&fifo->lock, flags);
105 	struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
118 	struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
183 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
184 	struct nvkm_instmem *imem = fifo->engine.subdev.device->imem;
186 	mutex_lock(&fifo->mutex);
188 	mutex_unlock(&fifo->mutex);
194 	struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
195 	struct nvkm_instmem *imem = fifo->engine.subdev.device->imem;
199 	mutex_lock(&fifo->mutex);
201 	mutex_unlock(&fifo->mutex);
212 nv04_fifo_pause(struct nvkm_fifo *fifo, unsigned long *pflags)
213 __acquires(fifo->lock)
215 	struct nvkm_device *device = fifo->engine.subdev.device;
218 	spin_lock_irqsave(&fifo->lock, flags);
247 nv04_fifo_start(struct nvkm_fifo *fifo, unsigned long *pflags)
248 __releases(fifo->lock)
250 	struct nvkm_device *device = fifo->engine.subdev.device;
256 	spin_unlock_irqrestore(&fifo->lock, flags);
303 nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get)
305 	struct nvkm_subdev *subdev = &fifo->engine.subdev;
330 		chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
354 nv04_fifo_intr_dma_pusher(struct nvkm_fifo *fifo, u32 chid)
356 	struct nvkm_subdev *subdev = &fifo->engine.subdev;
366 	chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
408 	struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth);
409 	struct nvkm_subdev *subdev = &fifo->engine.subdev;
418 	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;
422 		nv04_fifo_intr_cache_error(fifo, chid, get);
427 		nv04_fifo_intr_dma_pusher(fifo, chid);
450 			nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);
466 nv04_fifo_init(struct nvkm_fifo *fifo)
468 	struct nvkm_device *device = fifo->engine.subdev.device;
483 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
494 nv04_fifo_runl_ctor(struct nvkm_fifo *fifo)
498 	runl = nvkm_runl_new(fifo, 0, 0, 0);
502 	nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0);
503 	nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0);
504 	nvkm_runl_add(runl, 1, fifo->func->engn   , NVKM_ENGINE_GR, 0);
505 	nvkm_runl_add(runl, 2, fifo->func->engn   , NVKM_ENGINE_MPEG, 0); /* NV31- */
510 nv04_fifo_chid_ctor(struct nvkm_fifo *fifo, int nr)
513 	return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr - 1, &fifo->chid);
517 nv04_fifo_chid_nr(struct nvkm_fifo *fifo)