engine/disp/dp.c

45 nvkm_dp_mst_id_put(struct nvkm_outp *outp, u32 id)
51 nvkm_dp_mst_id_get(struct nvkm_outp *outp, u32 *pid)
53 	*pid = BIT(outp->index);
58 nvkm_dp_aux_xfer(struct nvkm_outp *outp, u8 type, u32 addr, u8 *data, u8 *size)
60 	int ret = nvkm_i2c_aux_acquire(outp->dp.aux);
65 	ret = nvkm_i2c_aux_xfer(outp->dp.aux, false, type, addr, data, size);
66 	nvkm_i2c_aux_release(outp->dp.aux);
71 nvkm_dp_aux_pwr(struct nvkm_outp *outp, bool pu)
73 	outp->dp.enabled = pu;
74 	nvkm_dp_enable(outp, outp->dp.enabled);
79 	struct nvkm_outp *outp;
94 	struct nvkm_outp *outp = lt->outp;
105 	ret = nvkm_rdaux(outp->dp.aux, addr, &lt->stat[0], 3);
114 	ret = nvkm_rdaux(outp->dp.aux, addr, &lt->stat[4], 2);
119 		ret = nvkm_rdaux(outp->dp.aux, DPCD_LS0C, &lt->pc2stat, 1);
123 		OUTP_TRACE(outp, "status %6ph pc2 %02x", lt->stat, lt->pc2stat);
125 		OUTP_TRACE(outp, "status %6ph", lt->stat);
134 	struct nvkm_outp *outp = lt->outp;
135 	struct nvkm_ior *ior = outp->ior;
166 		OUTP_TRACE(outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2);
171 		data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
189 	ret = nvkm_wraux(outp->dp.aux, addr, lt->conf, 4);
194 		ret = nvkm_wraux(outp->dp.aux, DPCD_LC0F, lt->pc2conf, 2);
205 	struct nvkm_outp *outp = lt->outp;
209 	OUTP_TRACE(outp, "training pattern %d", pattern);
210 	outp->ior->func->dp->pattern(outp->ior, pattern);
217 	nvkm_rdaux(outp->dp.aux, addr, &sink_tp, 1);
225 	nvkm_wraux(outp->dp.aux, addr, &sink_tp, 1);
231 	struct nvkm_i2c_aux *aux = lt->outp->dp.aux;
242 		if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 &&
243 		    lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)
246 		if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 &&
247 		    lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
252 		usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
262 		for (i = 0; i < lt->outp->ior->dp.nr && eq_done; i++) {
284 	if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater)
285 		usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
293 		for (i = 0; i < lt->outp->ior->dp.nr; i++) {
313 nvkm_dp_train_link(struct nvkm_outp *outp, int rate)
315 	struct nvkm_ior *ior = outp->ior;
317 		.outp = outp,
318 		.pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED,
319 		.repeaters = outp->dp.lttprs,
324 	OUTP_DBG(outp, "training %dx%02x", ior->dp.nr, ior->dp.bw);
327 	sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0;
331 	if (outp->dp.lt.post_adj)
334 	ret = nvkm_wraux(outp->dp.aux, DPCD_LC00_LINK_BW_SET, sink, 2);
338 	if (outp->dp.rate[rate].dpcd >= 0) {
339 		ret = nvkm_rdaux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
344 		sink[0] |= outp->dp.rate[rate].dpcd;
346 		ret = nvkm_wraux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
354 			OUTP_DBG(outp, "training LTTPR%d", lt.repeater);
356 			OUTP_DBG(outp, "training sink");
369 nvkm_dp_train_links(struct nvkm_outp *outp, int rate)
371 	struct nvkm_ior *ior = outp->ior;
372 	struct nvkm_disp *disp = outp->disp;
378 	OUTP_DBG(outp, "programming link for %dx%02x", ior->dp.nr, ior->dp.bw);
382 		outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED;
384 		outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
386 	if (AMPERE_IED_HACK(disp) && (lnkcmp = outp->dp.info.script[0])) {
392 		nvbios_init(&outp->disp->engine.subdev, lnkcmp,
393 			init.outp = &outp->info;
400 	if ((lnkcmp = outp->dp.info.lnkcmp)) {
401 		if (outp->dp.version < 0x30) {
412 			init.outp = &outp->info;
418 	ret = ior->func->dp->links(ior, outp->dp.aux);
421 			OUTP_ERR(outp, "train failed with %d", ret);
430 	return nvkm_dp_train_link(outp, rate);
434 nvkm_dp_train_fini(struct nvkm_outp *outp)
437 	nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[1],
438 		init.outp = &outp->info;
439 		init.or   = outp->ior->id;
440 		init.link = outp->ior->asy.link;
445 nvkm_dp_train_init(struct nvkm_outp *outp)
448 	if (outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
449 		nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[2],
450 			init.outp = &outp->info;
451 			init.or   = outp->ior->id;
452 			init.link = outp->ior->asy.link;
455 		nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[3],
456 			init.outp = &outp->info;
457 			init.or   = outp->ior->id;
458 			init.link = outp->ior->asy.link;
462 	if (!AMPERE_IED_HACK(outp->disp)) {
464 		nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[0],
465 			init.outp = &outp->info;
466 			init.or   = outp->ior->id;
467 			init.link = outp->ior->asy.link;
473 nvkm_dp_drive(struct nvkm_outp *outp, u8 lanes, u8 pe[4], u8 vs[4])
476 		.outp = outp,
487 nvkm_dp_train(struct nvkm_outp *outp, bool retrain)
489 	struct nvkm_ior *ior = outp->ior;
492 	for (rate = 0; rate < outp->dp.rates; rate++) {
493 		if (outp->dp.rate[rate].rate == (retrain ? ior->dp.bw : outp->dp.lt.bw) * 27000)
497 	if (WARN_ON(rate == outp->dp.rates))
502 		mutex_lock(&outp->dp.mutex);
503 		ret = nvkm_dp_train_link(outp, rate);
504 		mutex_unlock(&outp->dp.mutex);
508 	mutex_lock(&outp->dp.mutex);
509 	OUTP_DBG(outp, "training");
511 	ior->dp.mst = outp->dp.lt.mst;
512 	ior->dp.ef = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
513 	ior->dp.bw = outp->dp.lt.bw;
514 	ior->dp.nr = outp->dp.lt.nr;
516 	nvkm_dp_train_init(outp);
517 	ret = nvkm_dp_train_links(outp, rate);
518 	nvkm_dp_train_fini(outp);
520 		OUTP_ERR(outp, "training failed");
522 		OUTP_DBG(outp, "training done");
524 	mutex_unlock(&outp->dp.mutex);
529 nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)
532 	nvbios_init(&ior->disp->engine.subdev, outp->dp.info.script[4],
533 		init.outp = &outp->info;
540 nvkm_dp_release(struct nvkm_outp *outp)
542 	outp->ior->dp.nr = 0;
543 	nvkm_dp_disable(outp, outp->ior);
545 	nvkm_outp_release(outp);
549 nvkm_dp_enable(struct nvkm_outp *outp, bool auxpwr)
551 	struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio;
552 	struct nvkm_i2c_aux *aux = outp->dp.aux;
554 	if (auxpwr && !outp->dp.aux_pwr) {
559 		if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
563 				outp->dp.aux_pwr_pu = true;
576 		OUTP_DBG(outp, "aux power -> always");
578 		outp->dp.aux_pwr = true;
580 	if (!auxpwr && outp->dp.aux_pwr) {
581 		OUTP_DBG(outp, "aux power -> demand");
583 		outp->dp.aux_pwr = false;
588 		if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
589 			if (outp->dp.aux_pwr_pu) {
591 				outp->dp.aux_pwr_pu = false;
598 nvkm_dp_fini(struct nvkm_outp *outp)
600 	nvkm_dp_enable(outp, false);
604 nvkm_dp_init(struct nvkm_outp *outp)
606 	nvkm_outp_init(outp);
607 	nvkm_dp_enable(outp, outp->dp.enabled);
611 nvkm_dp_dtor(struct nvkm_outp *outp)
613 	return outp;
641 	struct nvkm_outp *outp;
647 	outp = *poutp;
652 		outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
654 		outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
655 	if (!outp->dp.aux) {
656 		OUTP_ERR(outp, "no aux");
661 	data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
662 				  &outp->dp.version, &hdr, &cnt, &len, &outp->dp.info);
664 		OUTP_ERR(outp, "no bios dp data");
668 	OUTP_DBG(outp, "bios dp %02x %02x %02x %02x", outp->dp.version, hdr, cnt, len);
671 	outp->dp.mst = data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
673 	mutex_init(&outp->dp.mutex);