engine/disp/dp.c

92 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
94 	struct nvkm_outp *outp = lt->outp;
100 	if (lt->repeater)
101 		addr = DPCD_LTTPR_LANE0_1_STATUS(lt->repeater);
105 	ret = nvkm_rdaux(outp->dp.aux, addr, &lt->stat[0], 3);
109 	if (lt->repeater)
110 		addr = DPCD_LTTPR_LANE0_1_ADJUST(lt->repeater);
114 	ret = nvkm_rdaux(outp->dp.aux, addr, &lt->stat[4], 2);
119 		ret = nvkm_rdaux(outp->dp.aux, DPCD_LS0C, &lt->pc2stat, 1);
121 			lt->pc2stat = 0x00;
123 		OUTP_TRACE(outp, "status %6ph pc2 %02x", lt->stat, lt->pc2stat);
125 		OUTP_TRACE(outp, "status %6ph", lt->stat);
132 nvkm_dp_train_drive(struct lt_state *lt, bool pc)
134 	struct nvkm_outp *outp = lt->outp;
145 		u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
146 		u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
163 		lt->conf[i] = (lpre << 3) | lvsw;
164 		lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
166 		OUTP_TRACE(outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2);
168 		if (lt->repeater != lt->repeaters)
184 	if (lt->repeater)
185 		addr = DPCD_LTTPR_LANE0_SET(lt->repeater);
189 	ret = nvkm_wraux(outp->dp.aux, addr, lt->conf, 4);
194 		ret = nvkm_wraux(outp->dp.aux, DPCD_LC0F, lt->pc2conf, 2);
203 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
205 	struct nvkm_outp *outp = lt->outp;
212 	if (lt->repeater)
213 		addr = DPCD_LTTPR_PATTERN_SET(lt->repeater);
229 nvkm_dp_train_eq(struct lt_state *lt)
231 	struct nvkm_i2c_aux *aux = lt->outp->dp.aux;
236 	if (lt->repeater) {
237 		if (!nvkm_rdaux(aux, DPCD_LTTPR_AUX_RD_INTERVAL(lt->repeater), &data, sizeof(data)))
240 		nvkm_dp_train_pattern(lt, 4);
242 		if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 &&
243 		    lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)
244 			nvkm_dp_train_pattern(lt, 4);
246 		if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 &&
247 		    lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
248 			nvkm_dp_train_pattern(lt, 3);
250 			nvkm_dp_train_pattern(lt, 2);
252 		usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
257 		    nvkm_dp_train_drive(lt, lt->pc2)) ||
258 		    nvkm_dp_train_sense(lt, lt->pc2, usec ? usec : 400))
261 		eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
262 		for (i = 0; i < lt->outp->ior->dp.nr && eq_done; i++) {
263 			u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
276 nvkm_dp_train_cr(struct lt_state *lt)
279 	int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
282 	nvkm_dp_train_pattern(lt, 1);
284 	if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater)
285 		usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
288 		if (nvkm_dp_train_drive(lt, false) ||
289 		    nvkm_dp_train_sense(lt, false, usec ? usec : 100))
293 		for (i = 0; i < lt->outp->ior->dp.nr; i++) {
294 			u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
297 				if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
303 		if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
304 			voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
316 	struct lt_state lt = {
331 	if (outp->dp.lt.post_adj)
352 	for (lt.repeater = lt.repeaters; lt.repeater >= 0; lt.repeater--) {
353 		if (lt.repeater)
354 			OUTP_DBG(outp, "training LTTPR%d", lt.repeater);
358 		memset(lt.stat, 0x00, sizeof(lt.stat));
359 		ret = nvkm_dp_train_cr(&lt);
361 			ret = nvkm_dp_train_eq(&lt);
362 		nvkm_dp_train_pattern(&lt, 0);
475 	struct lt_state lt = {
483 	return nvkm_dp_train_drive(&lt, false);
493 		if (outp->dp.rate[rate].rate == (retrain ? ior->dp.bw : outp->dp.lt.bw) * 27000)
511 	ior->dp.mst = outp->dp.lt.mst;
513 	ior->dp.bw = outp->dp.lt.bw;
514 	ior->dp.nr = outp->dp.lt.nr;