drm/nouveau/nv84_fence.c

36 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
38 	struct nvif_push *push = chan->chan.push;
41 		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
59 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
61 	struct nvif_push *push = chan->chan.push;
64 		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
80 nv84_fence_chid(struct nouveau_channel *chan)
82 	return chan->drm->runl[chan->runlist].chan_id_base + chan->chid;
88 	struct nouveau_channel *chan = fence->channel;
89 	struct nv84_fence_chan *fctx = chan->fence;
90 	u64 addr = fctx->vma->addr + nv84_fence_chid(chan) * 16;
92 	return fctx->base.emit32(chan, addr, fence->base.seqno);
97 		struct nouveau_channel *prev, struct nouveau_channel *chan)
99 	struct nv84_fence_chan *fctx = chan->fence;
102 	return fctx->base.sync32(chan, addr, fence->base.seqno);
106 nv84_fence_read(struct nouveau_channel *chan)
108 	struct nv84_fence_priv *priv = chan->drm->fence;
109 	return nouveau_bo_rd32(priv->bo, nv84_fence_chid(chan) * 16/4);
113 nv84_fence_context_del(struct nouveau_channel *chan)
115 	struct nv84_fence_priv *priv = chan->drm->fence;
116 	struct nv84_fence_chan *fctx = chan->fence;
118 	nouveau_bo_wr32(priv->bo, nv84_fence_chid(chan) * 16 / 4, fctx->base.sequence);
123 	chan->fence = NULL;
128 nv84_fence_context_new(struct nouveau_channel *chan)
130 	struct nv84_fence_priv *priv = chan->drm->fence;
134 	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
138 	nouveau_fence_context_new(chan, &fctx->base);
144 	fctx->base.sequence = nv84_fence_read(chan);
147 	ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
151 		nv84_fence_context_del(chan);