nouveau/dispnv50/disp.c

371 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
373 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;
381 		asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
384 		while (asyh->or.bpc > 6) {
385 			mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
389 			asyh->or.bpc -= 2;
404 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
413 		asyh->or.bpc = connector->display_info.bpc;
488 	struct nv50_head_atom *asyh =
508 	core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
509 	asyh->or.depth = 0;
968 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
988 		asyh->or.bpc = connector->display_info.bpc;
989 		asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
1003 	slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
1007 	asyh->dp.tu = slots;
1028 	struct nv50_head_atom *asyh =
1064 	mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1065 			   nv50_dp_bpc_to_depth(asyh->or.bpc));
1538 		struct nv50_head_atom *asyh, u8 proto, u8 depth)
1543 	if (!asyh) {
1550 		asyh->or.depth = depth;
1553 	core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1606 			  struct nv50_head *head, struct nv50_head_atom *asyh)
1621 	unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1622 	unsigned rasterWidth = asyh->mode.h.active;
1623 	unsigned depth = asyh->or.bpc * 3;
1625 	u64 pixelClockHz = asyh->mode.clock * 1000;
1745 	struct nv50_head_atom *asyh =
1747 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1819 			if (asyh->or.bpc == 8)
1826 		nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1827 		nv50_sor_dp_watermark_sst(nv_encoder, head, asyh);
1828 		depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1851 	nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1982 	struct nv50_head_atom *asyh =
1995 	switch (asyh->or.bpc) {
1996 	case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1997 	case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1998 	case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1999 	default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
2011 		nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6);
2018 	core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2195 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2199 			  asyh->clr.mask, asyh->set.mask);
2206 		if (asyh->clr.mask) {
2207 			nv50_head_flush_clr(head, asyh, atom->flush_disable);
2278 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2282 			  asyh->set.mask, asyh->clr.mask);
2284 		if (asyh->set.mask) {
2285 			nv50_head_flush_set(head, asyh);
2329 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2333 			  asyh->set.mask, asyh->clr.mask);
2335 		if (asyh->set.mask) {
2336 			nv50_head_flush_set_wndw(head, asyh);
2569 	struct nv50_head_atom *asyh;
2580 			asyh = nv50_head_atom(new_crtc_state);
2581 			core->func->head->static_wndw_map(head, asyh);