Lines Matching defs:regp
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
87 regp->ramdac_634 = level;
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
126 struct nvkm_pll_vals *pv = ®p->pllvals;
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
308 regp->MiscOutReg = 0x23;
310 regp->MiscOutReg |= 0x40;
312 regp->MiscOutReg |= 0x80;
320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
322 regp->MiscOutReg = 0x63; /* -hsync +vsync */
324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
326 regp->MiscOutReg = 0x23; /* +hsync +vsync */
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
390 regp->CRTC[NV_CIO_CRE_42] =
392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
428 regp->Attribute[0] = 0x00; /* standard colormap translation */
429 regp->Attribute[1] = 0x01;
430 regp->Attribute[2] = 0x02;
431 regp->Attribute[3] = 0x03;
432 regp->Attribute[4] = 0x04;
433 regp->Attribute[5] = 0x05;
434 regp->Attribute[6] = 0x06;
435 regp->Attribute[7] = 0x07;
436 regp->Attribute[8] = 0x08;
437 regp->Attribute[9] = 0x09;
438 regp->Attribute[10] = 0x0A;
439 regp->Attribute[11] = 0x0B;
440 regp->Attribute[12] = 0x0C;
441 regp->Attribute[13] = 0x0D;
442 regp->Attribute[14] = 0x0E;
443 regp->Attribute[15] = 0x0F;
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
496 regp->crtc_eng_ctrl = 0;
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
519 regp->CRTC[NV_CIO_CRE_53] = 0;
520 regp->CRTC[NV_CIO_CRE_54] = 0;
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
557 regp->crtc_830 = mode->crtc_vdisplay - 3;
558 regp->crtc_834 = mode->crtc_vdisplay - 1;
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
574 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
575 regp->CRTC[NV_CIO_CRE_86] = 0x1;
578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
587 regp->nv10_cursync = (1 << 25);
589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
598 regp->tv_setup = 0;
603 regp->ramdac_8c0 = 0x100;
604 regp->ramdac_a20 = 0x0;
605 regp->ramdac_a24 = 0xfffff;
606 regp->ramdac_a34 = 0x1;
832 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
864 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
865 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
867 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
868 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
870 regp->ramdac_gen_ctrl);
872 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
873 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
875 regp->CRTC[NV_CIO_CRE_42] =
877 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
878 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
879 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
882 regp->fb_start = nv_crtc->fb.offset & ~3;
883 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
884 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
890 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
891 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
893 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
896 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
897 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);