drm/msm/msm_mdss.c

19 #include "msm_mdss.h"
34 struct msm_mdss {
52 					    struct msm_mdss *msm_mdss)
62 	msm_mdss->mdp_path[0] = path0;
63 	msm_mdss->num_mdp_paths = 1;
67 		msm_mdss->mdp_path[1] = path1;
68 		msm_mdss->num_mdp_paths++;
73 		msm_mdss->reg_bus_path = reg_bus_path;
80 	struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
86 	interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
92 		rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
95 			dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
108 	struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
112 	clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
119 	struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
123 	set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
129 	.name = "msm_mdss",
139 	struct msm_mdss *msm_mdss = domain->host_data;
144 	return irq_set_chip_data(irq, msm_mdss);
152 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
157 	dev = msm_mdss->dev;
160 			&msm_mdss_irqdomain_ops, msm_mdss);
166 	msm_mdss->irq_controller.enabled_mask = 0;
167 	msm_mdss->irq_controller.domain = domain;
172 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
174 	const struct msm_mdss_data *data = msm_mdss->mdss_data;
176 	writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
179 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
181 	const struct msm_mdss_data *data = msm_mdss->mdss_data;
192 	writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
195 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
197 	const struct msm_mdss_data *data = msm_mdss->mdss_data;
203 	writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
206 		writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
207 		writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
210 			writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
212 			writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
213 		writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
229 static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
262 	struct msm_mdss *mdss;
279 static int msm_mdss_enable(struct msm_mdss *msm_mdss)
288 	for (i = 0; i < msm_mdss->num_mdp_paths; i++)
289 		icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
291 	if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
292 		icc_set_bw(msm_mdss->reg_bus_path, 0,
293 			   msm_mdss->mdss_data->reg_bus_bw);
295 		icc_set_bw(msm_mdss->reg_bus_path, 0,
298 	ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
300 		dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
308 	if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
318 	switch (msm_mdss->mdss_data->ubwc_dec_version) {
324 		msm_mdss_setup_ubwc_dec_20(msm_mdss);
327 		msm_mdss_setup_ubwc_dec_30(msm_mdss);
331 		msm_mdss_setup_ubwc_dec_40(msm_mdss);
334 		dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
335 			msm_mdss->mdss_data->ubwc_dec_version);
336 		dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
337 			readl_relaxed(msm_mdss->mmio + HW_REV));
338 		dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
339 			readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
346 static int msm_mdss_disable(struct msm_mdss *msm_mdss)
350 	clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
352 	for (i = 0; i < msm_mdss->num_mdp_paths; i++)
353 		icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
355 	if (msm_mdss->reg_bus_path)
356 		icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
361 static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
363 	struct platform_device *pdev = to_platform_device(msm_mdss->dev);
366 	pm_runtime_suspend(msm_mdss->dev);
367 	pm_runtime_disable(msm_mdss->dev);
368 	irq_domain_remove(msm_mdss->irq_controller.domain);
369 	msm_mdss->irq_controller.domain = NULL;
430 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
432 	struct msm_mdss *msm_mdss;
440 	msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
441 	if (!msm_mdss)
444 	msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
446 	msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
447 	if (IS_ERR(msm_mdss->mmio))
448 		return ERR_CAST(msm_mdss->mmio);
450 	dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
452 	ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
457 		ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
459 		ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
464 	msm_mdss->num_clocks = ret;
465 	msm_mdss->is_mdp5 = is_mdp5;
467 	msm_mdss->dev = &pdev->dev;
473 	ret = _msm_mdss_irq_domain_add(msm_mdss);
478 					 msm_mdss);
482 	return msm_mdss;
487 	struct msm_mdss *mdss = dev_get_drvdata(dev);
496 	struct msm_mdss *mdss = dev_get_drvdata(dev);
527 	struct msm_mdss *mdss;
556 	struct msm_mdss *mdss = platform_get_drvdata(pdev);