dsi/phy/dsi_phy_28nm.c

72 	struct msm_dsi_phy *phy;
86 		val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
101 	void __iomem *base = pll_28nm->phy->pll_base;
119 	struct device *dev = &pll_28nm->phy->pdev->dev;
120 	void __iomem *base = pll_28nm->phy->pll_base;
211 	if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
244 	void __iomem *base = pll_28nm->phy->pll_base;
290 	struct device *dev = &pll_28nm->phy->pdev->dev;
291 	void __iomem *base = pll_28nm->phy->pll_base;
297 	DBG("id=%d", pll_28nm->phy->id);
367 	if (unlikely(pll_28nm->phy->pll_on))
373 			pll_28nm->phy->pll_on = true;
384 	struct device *dev = &pll_28nm->phy->pdev->dev;
385 	void __iomem *base = pll_28nm->phy->pll_base;
391 	DBG("id=%d", pll_28nm->phy->id);
452 	struct device *dev = &pll_28nm->phy->pdev->dev;
453 	void __iomem *base = pll_28nm->phy->pll_base;
458 	DBG("id=%d", pll_28nm->phy->id);
460 	if (unlikely(pll_28nm->phy->pll_on))
493 	pll_28nm->phy->pll_on = true;
502 	DBG("id=%d", pll_28nm->phy->id);
504 	if (unlikely(!pll_28nm->phy->pll_on))
507 	dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
509 	pll_28nm->phy->pll_on = false;
517 	if      (rate < pll_28nm->phy->cfg->min_pll_rate)
518 		return  pll_28nm->phy->cfg->min_pll_rate;
519 	else if (rate > pll_28nm->phy->cfg->max_pll_rate)
520 		return  pll_28nm->phy->cfg->max_pll_rate;
556 static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy)
558 	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
560 	void __iomem *base = pll_28nm->phy->pll_base;
567 	if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
568 		cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
573 static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)
575 	struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw);
577 	void __iomem *base = pll_28nm->phy->pll_base;
580 	ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw,
583 		DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev,
609 	struct device *dev = &pll_28nm->phy->pdev->dev;
613 	DBG("%d", pll_28nm->phy->id);
615 	if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
617 	else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226)
622 	snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id);
628 	snprintf(clk_name, sizeof(clk_name), "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
631 			pll_28nm->phy->pll_base +
637 	snprintf(clk_name, sizeof(clk_name), "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);
643 	snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id);
645 			&pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base +
652 	snprintf(clk_name, sizeof(clk_name), "dsi%dbyte_mux", pll_28nm->phy->id);
657 			}), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
662 	snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id);
672 static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
674 	struct platform_device *pdev = phy->pdev;
685 	pll_28nm->phy = phy;
687 	ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
693 	phy->vco_hw = &pll_28nm->clk_hw;
698 static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
701 	void __iomem *base = phy->base;
731 static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy)
733 	void __iomem *base = phy->reg_base;
743 	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
746 static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
748 	void __iomem *base = phy->reg_base;
758 	if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
759 		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05);
761 		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d);
764 static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
767 		dsi_phy_write(phy->reg_base +
772 	if (phy->regulator_ldo_mode)
773 		dsi_28nm_phy_regulator_enable_ldo(phy);
775 		dsi_28nm_phy_regulator_enable_dcdc(phy);
778 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
781 	struct msm_dsi_dphy_timing *timing = &phy->timing;
783 	void __iomem *base = phy->base;
789 		DRM_DEV_ERROR(&phy->pdev->dev,
797 	dsi_28nm_phy_regulator_ctrl(phy, true);
799 	dsi_28nm_dphy_set_timing(phy, timing);
826 	if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
835 static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
837 	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);
838 	dsi_28nm_phy_regulator_ctrl(phy, false);
842 	 * ensure that the phy is completely disabled