msm/dp/dp_ctrl.c

45 	u64 pclk_khz;    /* in KHz */
313 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
316 	int nlanes = in->nlanes;
317 	int dsc_num_slices = in->num_of_dsc_slices;
332 	tu->lclk_fp              = drm_fixp_from_fraction(in->lclk, 1);
333 	tu->pclk_fp              = drm_fixp_from_fraction(in->pclk_khz, 1000);
334 	tu->lwidth               = in->hactive;
335 	tu->hbp_relative_to_pclk = in->hporch;
336 	tu->nlanes               = in->nlanes;
337 	tu->bpp                  = in->bpp;
338 	tu->pixelEnc             = in->pixel_enc;
339 	tu->dsc_en               = in->dsc_en;
340 	tu->async_en             = in->async_en;
341 	tu->lwidth_fp            = drm_fixp_from_fraction(in->hactive, 1);
342 	tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
371 	if (!in->dsc_en)
374 	temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
375 	temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
413 	if (in->fec_en) {
626 				struct dp_tu_calc_input *in,
648 	dp_panel_update_tu_timings(in, tu);
962 	struct dp_tu_calc_input in;
967 	in.lclk = ctrl->link->link_params.rate / 1000;
968 	in.pclk_khz = drm_mode->clock;
969 	in.hactive = drm_mode->hdisplay;
970 	in.hporch = drm_mode->htotal - drm_mode->hdisplay;
971 	in.nlanes = ctrl->link->link_params.num_lanes;
972 	in.bpp = ctrl->panel->dp_mode.bpp;
973 	in.pixel_enc = ctrl->panel->dp_mode.out_fmt_is_yuv_420 ? 420 : 444;
974 	in.dsc_en = 0;
975 	in.async_en = 0;
976 	in.fec_en = 0;
977 	in.num_of_dsc_slices = 0;
978 	in.compress_ratio = 100;
980 	_dp_ctrl_calc_tu(ctrl, &in, tu_table);
1792 	 * only interested in the lane number after reduced
1793 	 * lane_count = 4, then only interested in 2 lanes
1794 	 * lane_count = 2, then only interested in 1 lane
1867 			if (rc < 0) { /* already in RBR = 1.6G */
2227 		dev_err(dev, "invalid DP OPP table in device tree\n");
2241 	/* in parameters */