Lines Matching defs:lm
128 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
132 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
221 uint32_t lm = mixer->lm;
223 uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
330 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
332 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
334 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
346 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
347 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
368 uint32_t lm = mixer->lm;
385 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
390 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
392 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
395 u32 r_lm = r_mixer->lm;
749 if (mode->hdisplay > hw_cfg->lm.max_width)
770 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
778 pstates[i].state->stage = hw_cfg->lm.nb_stages;
889 int lm;
893 lm = mdp5_cstate->pipeline.mixer->lm;
924 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
925 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
927 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
930 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
933 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
936 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
939 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
944 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
1227 dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1228 mdp5_cstate->pipeline.mixer->lm);