disp/dpu1/dpu_plane.c

576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
606 	_dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation);
620 	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
635 	_dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
638 	if (pstate->r_pipe.sspp)
639 		_dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
648 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
659 	pstate->aspace = kms->base.aspace;
668 	if (pstate->aspace) {
670 				pstate->aspace, pstate->needs_dirtyfb);
678 	ret = dpu_format_populate_layout(pstate->aspace,
797 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
798 	struct dpu_sw_pipe *pipe = &pstate->pipe;
799 	struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
802 	struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
803 	struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
808 	const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
809 	const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk;
833 	pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
834 	if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
940 	pstate->rotation = rotation;
941 	pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
971 	struct dpu_plane_state *pstate;
979 	pstate = to_dpu_plane_state(plane->state);
992 		dpu_plane_flush_csc(pdpu, &pstate->pipe);
993 		dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
998 		pstate->pending = false;
1027 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1047 	_dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation);
1054 		unsigned int rotation = pstate->rotation;
1084 	if (pstate->needs_qos_remap)
1092 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1093 	struct dpu_sw_pipe *pipe = &pstate->pipe;
1094 	struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1100 	struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1101 	struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1114 	pstate->pending = true;
1117 	pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
1135 	if (pstate->needs_qos_remap)
1136 		pstate->needs_qos_remap = false;
1138 	pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1141 	pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
1144 		pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1146 		pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
1153 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1154 	struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1157 				pstate->pipe.multirect_mode);
1167 	pstate->pending = true;
1199 	struct dpu_plane_state *pstate;
1212 	pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1213 	if (!pstate) {
1220 	pstate->pending = false;
1222 	__drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1224 	return &pstate->base;
1258 	const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1259 	const struct dpu_sw_pipe *pipe = &pstate->pipe;
1260 	const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1261 	const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1262 	const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1264 	drm_printf(p, "\tstage=%d\n", pstate->stage);
1287 	struct dpu_plane_state *pstate;
1304 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1305 	if (!pstate) {
1314 	pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
1315 	pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
1316 	pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1318 	pstate->r_pipe.sspp = NULL;
1320 	__drm_atomic_helper_plane_reset(plane, &pstate->base);
1327 	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
1334 	_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
1335 	if (pstate->r_pipe.sspp)
1336 		_dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);