Lines Matching refs:catalog
76 * @catalog: Points to dpu catalog structure
87 const struct dpu_mdss_cfg *catalog;
107 * @catalog: Points to dpu catalog structure
115 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
135 hw_latency_lines = catalog->perf->min_prefill_lines;
213 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
272 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
273 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage];
274 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage];
835 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
837 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
864 max_linewidth = pdpu->catalog->caps->max_linewidth;
1072 const struct dpu_perf_cfg *perf = pdpu->catalog->perf;
1139 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1145 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1408 pdpu->catalog = kms->catalog;