disp/dpu1/dpu_hw_interrupts.c

209 static inline struct dpu_hw_intr_entry *dpu_core_irq_get_entry(struct dpu_hw_intr *intr,
212 	return &intr->irq_tbl[irq_idx - 1];
241 	struct dpu_hw_intr *intr = dpu_kms->hw_intr;
249 	if (!intr)
252 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
254 		if (!test_bit(reg_idx, &intr->irq_mask))
258 		irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
261 		enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
265 			DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
275 		 * Search through matching intr status.
294 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
299 static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr,
307 	if (!intr)
321 	assert_spin_locked(&intr->irq_lock);
324 	reg = &intr->intr_set[reg_idx];
330 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
338 		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
340 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
345 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
355 static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr,
363 	if (!intr)
377 	assert_spin_locked(&intr->irq_lock);
380 	reg = &intr->intr_set[reg_idx];
382 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
390 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
392 		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
397 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
409 	struct dpu_hw_intr *intr = dpu_kms->hw_intr;
412 	if (!intr)
416 		if (test_bit(i, &intr->irq_mask))
417 			DPU_REG_WRITE(&intr->hw,
418 					intr->intr_set[i].clr_off, 0xffffffff);
427 	struct dpu_hw_intr *intr = dpu_kms->hw_intr;
430 	if (!intr)
434 		if (test_bit(i, &intr->irq_mask))
435 			DPU_REG_WRITE(&intr->hw,
436 					intr->intr_set[i].en_off, 0x00000000);
446 	struct dpu_hw_intr *intr = dpu_kms->hw_intr;
451 	if (!intr)
459 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
462 	intr_status = DPU_REG_READ(&intr->hw,
463 			intr->intr_set[reg_idx].status_off) &
466 		DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
472 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
481 	struct dpu_hw_intr *intr;
487 	intr = drmm_kzalloc(dev, sizeof(*intr), GFP_KERNEL);
488 	if (!intr)
492 		intr->intr_set = dpu_intr_set_7xxx;
494 		intr->intr_set = dpu_intr_set_legacy;
496 	intr->hw.blk_addr = addr + m->mdp[0].base;
498 	intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
507 		intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
510 			intr->irq_mask |= BIT(DPU_IRQ_REG(intf->intr_tear_rd_ptr));
513 	spin_lock_init(&intr->irq_lock);
515 	return intr;