disp/dpu1/dpu_hw_dsc_1_2.c

83 	DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0);
84 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0);
127 	DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, data);
155 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, data);
160 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_PICTURE_SIZE, data);
165 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_SLICE_SIZE, data);
167 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE,
173 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_HRD_DELAYS, data);
175 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE,
181 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE_INC_DEC, data);
186 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_1, data);
191 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_2, data);
196 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_3, data);
201 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_4, data);
208 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_FLATNESS_QP, data);
210 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MODEL_SIZE,
219 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_CONFIG, data);
262 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_0,
267 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_1,
272 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_2,
277 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_3,
288 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_0,
294 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_0,
300 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_0,
307 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_1,
313 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_1,
319 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_1,
326 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_2,
332 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_2,
338 	DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_2,