80 static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
82 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
87 static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
89 	trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
90 				       dpu_hw_ctl_get_flush_register(ctx));
91 	DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
94 static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx)
96 	return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0));
99 static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
101 	trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
102 					 dpu_hw_ctl_get_flush_register(ctx));
103 	DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
106 static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
108 	trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
109 				     dpu_hw_ctl_get_flush_register(ctx));
110 	ctx->pending_flush_mask = 0x0;
111 	ctx->pending_intf_flush_mask = 0;
112 	ctx->pending_wb_flush_mask = 0;
113 	ctx->pending_merge_3d_flush_mask = 0;
114 	ctx->pending_dsc_flush_mask = 0;
115 	ctx->pending_cdm_flush_mask = 0;
117 	memset(ctx->pending_dspp_flush_mask, 0,
118 		sizeof(ctx->pending_dspp_flush_mask));
121 static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
125 					      ctx->pending_flush_mask);
126 	ctx->pending_flush_mask |= flushbits;
129 static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
131 	return ctx->pending_flush_mask;
134 static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
138 	if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
139 		DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
140 				ctx->pending_merge_3d_flush_mask);
141 	if (ctx->pending_flush_mask & BIT(INTF_IDX))
142 		DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
143 				ctx->pending_intf_flush_mask);
144 	if (ctx->pending_flush_mask & BIT(WB_IDX))
145 		DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH,
146 				ctx->pending_wb_flush_mask);
148 	if (ctx->pending_flush_mask & BIT(DSPP_IDX))
150 			if (ctx->pending_dspp_flush_mask[dspp - DSPP_0])
151 				DPU_REG_WRITE(&ctx->hw,
153 				ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
156 	if (ctx->pending_flush_mask & BIT(PERIPH_IDX))
157 		DPU_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH,
158 			      ctx->pending_periph_flush_mask);
160 	if (ctx->pending_flush_mask & BIT(DSC_IDX))
161 		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,
162 			      ctx->pending_dsc_flush_mask);
164 	if (ctx->pending_flush_mask & BIT(CDM_IDX))
165 		DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH,
166 			      ctx->pending_cdm_flush_mask);
168 	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
171 static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
173 	trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
174 				     dpu_hw_ctl_get_flush_register(ctx));
175 	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
178 static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx,
183 		ctx->pending_flush_mask |=  BIT(0);
186 		ctx->pending_flush_mask |= BIT(1);
189 		ctx->pending_flush_mask |= BIT(2);
192 		ctx->pending_flush_mask |= BIT(18);
195 		ctx->pending_flush_mask |= BIT(3);
198 		ctx->pending_flush_mask |= BIT(4);
201 		ctx->pending_flush_mask |= BIT(5);
204 		ctx->pending_flush_mask |= BIT(19);
207 		ctx->pending_flush_mask |= BIT(11);
210 		ctx->pending_flush_mask |= BIT(12);
213 		ctx->pending_flush_mask |= BIT(24);
216 		ctx->pending_flush_mask |= BIT(25);
219 		ctx->pending_flush_mask |= BIT(13);
222 		ctx->pending_flush_mask |= BIT(14);
225 		ctx->pending_flush_mask |= BIT(22);
228 		ctx->pending_flush_mask |= BIT(23);
235 static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
240 		ctx->pending_flush_mask |= BIT(6);
243 		ctx->pending_flush_mask |= BIT(7);
246 		ctx->pending_flush_mask |= BIT(8);
249 		ctx->pending_flush_mask |= BIT(9);
252 		ctx->pending_flush_mask |= BIT(10);
255 		ctx->pending_flush_mask |= BIT(20);
261 	ctx->pending_flush_mask |= CTL_FLUSH_MASK_CTL;
264 static void dpu_hw_ctl_update_pending_flush_intf(struct dpu_hw_ctl *ctx,
269 		ctx->pending_flush_mask |= BIT(31);
272 		ctx->pending_flush_mask |= BIT(30);
275 		ctx->pending_flush_mask |= BIT(29);
278 		ctx->pending_flush_mask |= BIT(28);
285 static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx,
292 		ctx->pending_flush_mask |= BIT(WB_IDX);
299 static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)
303 		ctx->pending_flush_mask |= BIT(CDM_IDX);
306 static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx,
309 	ctx->pending_wb_flush_mask |= BIT(wb - WB_0);
310 	ctx->pending_flush_mask |= BIT(WB_IDX);
313 static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,
316 	ctx->pending_intf_flush_mask |= BIT(intf - INTF_0);
317 	ctx->pending_flush_mask |= BIT(INTF_IDX);
320 static void dpu_hw_ctl_update_pending_flush_periph_v1(struct dpu_hw_ctl *ctx,
323 	ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
324 	ctx->pending_flush_mask |= BIT(PERIPH_IDX);
327 static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
330 	ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0);
331 	ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);
334 static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx,
337 	ctx->pending_dsc_flush_mask |= BIT(dsc_num - DSC_0);
338 	ctx->pending_flush_mask |= BIT(DSC_IDX);
341 static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)
343 	ctx->pending_cdm_flush_mask |= BIT(cdm_num - CDM_0);
344 	ctx->pending_flush_mask |= BIT(CDM_IDX);
347 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
352 		ctx->pending_flush_mask |= BIT(13);
355 		ctx->pending_flush_mask |= BIT(14);
358 		ctx->pending_flush_mask |= BIT(15);
361 		ctx->pending_flush_mask |= BIT(21);
369 	struct dpu_hw_ctl *ctx,	enum dpu_dspp dspp, u32 dspp_sub_blk)
376 		ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4);
382 	ctx->pending_flush_mask |= BIT(DSPP_IDX);
385 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
387 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
407 static int dpu_hw_ctl_reset_control(struct dpu_hw_ctl *ctx)
409 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
411 	pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
413 	if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US))
419 static int dpu_hw_ctl_wait_reset_status(struct dpu_hw_ctl *ctx)
421 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
429 	pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
430 	if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US)) {
431 		pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
438 static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
440 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
443 	for (i = 0; i < ctx->mixer_count; i++) {
444 		enum dpu_lm mixer_id = ctx->mixer_hw_caps[i].id;
480 static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
483 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
490 	stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
495 		&ctx->mixer_hw_caps->features))
538 	if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
543 static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
546 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
555 	if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
585 static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
588 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
618 static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
621 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
643 	dpu_hw_ctl_clear_all_blendstages(ctx);
670 static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
684 	DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);

Indexes created Fri Apr 26 00:00:17 MDT 2024