disp/dpu1/dpu_encoder_phys_vid.c

45 		struct dpu_hw_intf_timing_params *timing)
47 	memset(timing, 0, sizeof(*timing));
74 	timing->width = mode->hdisplay;	/* active width */
75 	timing->height = mode->vdisplay;	/* active height */
76 	timing->xres = timing->width;
77 	timing->yres = timing->height;
78 	timing->h_back_porch = mode->htotal - mode->hsync_end;
79 	timing->h_front_porch = mode->hsync_start - mode->hdisplay;
80 	timing->v_back_porch = mode->vtotal - mode->vsync_end;
81 	timing->v_front_porch = mode->vsync_start - mode->vdisplay;
82 	timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
83 	timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
84 	timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
85 	timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
86 	timing->border_clr = 0;
87 	timing->underflow_clr = 0xff;
88 	timing->hsync_skew = mode->hskew;
92 		timing->hsync_polarity = 0;
93 		timing->vsync_polarity = 0;
98 		timing->h_back_porch += timing->h_front_porch;
99 		timing->h_front_porch = 0;
100 		timing->v_back_porch += timing->v_front_porch;
101 		timing->v_front_porch = 0;
104 	timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
105 	timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
111 	if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
112 		timing->width = timing->width >> 1;
113 		timing->xres = timing->xres >> 1;
114 		timing->h_back_porch = timing->h_back_porch >> 1;
115 		timing->h_front_porch = timing->h_front_porch >> 1;
116 		timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
120 static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
122 	u32 active = timing->xres;
124 	    timing->h_back_porch + timing->h_front_porch +
125 	    timing->hsync_pulse_width;
129 static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
131 	u32 active = timing->yres;
133 	    timing->v_back_porch + timing->v_front_porch +
134 	    timing->vsync_pulse_width;
141  * @timing: Pointer to the intf timing information for the requested mode
154 		const struct dpu_hw_intf_timing_params *timing)
159 	    timing->v_back_porch + timing->vsync_pulse_width;
168 	} else if (timing->v_front_porch < needed_vfp_lines) {
174 		actual_vfp_lines = timing->v_front_porch;
182 		timing->v_front_porch, timing->v_back_porch,
183 		timing->vsync_pulse_width);
199  * @timing: Pointer to the intf timing information for the requested mode
202 				      const struct dpu_hw_intf_timing_params *timing)
214 	vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
216 		vert_total = get_vertical_total(timing);
217 		horiz_total = get_horizontal_total(timing);
251 		DPU_ERROR("timing engine setup is not supported\n");
460 	/* ctl_flush & timing engine enable will be triggered by framework */
592 	 * Wait for a vsync if timing en status is on after timing engine
618 	 * Video mode must flush CTL before enabling timing engine