Lines Matching refs:dpu_enc
227 struct dpu_encoder_virt *dpu_enc;
232 dpu_enc = to_dpu_encoder_virt(drm_enc);
233 info = &dpu_enc->connector->display_info;
245 struct dpu_encoder_virt *dpu_enc;
251 dpu_enc = to_dpu_encoder_virt(drm_enc);
252 disp_info = &dpu_enc->disp_info;
262 const struct dpu_encoder_virt *dpu_enc;
267 dpu_enc = to_dpu_encoder_virt(drm_enc);
268 disp_info = &dpu_enc->disp_info;
281 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
283 return dpu_enc->dsc ? true : false;
288 struct dpu_encoder_virt *dpu_enc;
291 dpu_enc = to_dpu_encoder_virt(drm_enc);
293 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
294 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
306 struct dpu_encoder_virt *dpu_enc;
310 dpu_enc = to_dpu_encoder_virt(drm_enc);
312 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
313 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
324 struct dpu_encoder_virt *dpu_enc;
333 dpu_enc = to_dpu_encoder_virt(drm_enc);
335 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
336 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
482 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
483 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
489 struct dpu_encoder_virt *dpu_enc;
493 dpu_enc = to_dpu_encoder_virt(drm_enc);
494 phys = dpu_enc ? dpu_enc->cur_master : NULL;
506 struct dpu_encoder_virt *dpu_enc;
516 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
518 disp_info = &dpu_enc->disp_info;
544 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
553 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
557 if (dpu_enc->phys_encs[i])
561 if (dpu_enc->dsc)
570 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
571 int index = dpu_enc->disp_info.h_tile_instance[0];
573 if (dpu_enc->disp_info.intf_type == INTF_DSI)
580 struct dpu_encoder_virt *dpu_enc,
590 if (dpu_enc->phys_encs[i])
636 struct dpu_encoder_virt *dpu_enc;
653 dpu_enc = to_dpu_encoder_virt(drm_enc);
654 DPU_DEBUG_ENC(dpu_enc, "\n");
657 disp_info = &dpu_enc->disp_info;
668 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);
685 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm)
687 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm)
706 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
717 if (!dpu_enc || !disp_info) {
718 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
719 dpu_enc != NULL, disp_info != NULL);
721 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
723 dpu_enc->num_phys_encs,
724 (int) ARRAY_SIZE(dpu_enc->hw_pp));
728 drm_enc = &dpu_enc->base;
741 for (i = 0; i < dpu_enc->num_phys_encs; i++)
742 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
744 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
745 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
754 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
755 phys_enc = dpu_enc->phys_encs[i];
766 struct dpu_encoder_virt *dpu_enc;
774 dpu_enc = to_dpu_encoder_virt(drm_enc);
776 DPU_DEBUG_ENC(dpu_enc, "\n");
777 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
778 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
786 struct dpu_encoder_virt *dpu_enc;
794 dpu_enc = to_dpu_encoder_virt(drm_enc);
796 DPU_DEBUG_ENC(dpu_enc, "\n");
797 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
798 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
808 struct dpu_encoder_virt *dpu_enc;
810 dpu_enc = to_dpu_encoder_virt(drm_enc);
816 if (!dpu_enc->cur_master) {
832 struct dpu_encoder_virt *dpu_enc;
834 dpu_enc = to_dpu_encoder_virt(drm_enc);
840 if (!dpu_enc->cur_master) {
855 struct dpu_encoder_virt *dpu_enc;
863 dpu_enc = to_dpu_encoder_virt(drm_enc);
865 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
871 if (!dpu_enc->idle_pc_supported &&
877 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
878 dpu_enc->rc_state, "begin");
883 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
884 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
887 mutex_lock(&dpu_enc->rc_lock);
890 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
893 mutex_unlock(&dpu_enc->rc_lock);
895 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
896 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
899 dpu_enc->rc_state);
900 mutex_unlock(&dpu_enc->rc_lock);
904 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
909 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
912 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
915 mutex_unlock(&dpu_enc->rc_lock);
925 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
928 dpu_enc->rc_state);
942 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
943 msecs_to_jiffies(dpu_enc->idle_timeout));
946 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
952 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
953 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
956 mutex_lock(&dpu_enc->rc_lock);
959 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
963 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
964 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
967 dpu_enc->rc_state);
968 mutex_unlock(&dpu_enc->rc_lock);
972 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
975 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
978 mutex_unlock(&dpu_enc->rc_lock);
982 mutex_lock(&dpu_enc->rc_lock);
985 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
988 mutex_unlock(&dpu_enc->rc_lock);
990 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
992 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
993 mutex_unlock(&dpu_enc->rc_lock);
1001 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
1004 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
1007 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1010 mutex_unlock(&dpu_enc->rc_lock);
1014 mutex_lock(&dpu_enc->rc_lock);
1016 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1018 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1019 mutex_unlock(&dpu_enc->rc_lock);
1027 if (dpu_enc->frame_busy_mask[0]) {
1029 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1030 mutex_unlock(&dpu_enc->rc_lock);
1039 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
1042 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1045 mutex_unlock(&dpu_enc->rc_lock);
1052 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1058 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1066 struct dpu_encoder_virt *dpu_enc;
1069 dpu_enc = to_dpu_encoder_virt(drm_enc);
1071 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1072 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1083 struct dpu_encoder_virt *dpu_enc;
1086 dpu_enc = to_dpu_encoder_virt(drm_enc);
1088 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1089 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1101 struct dpu_encoder_virt *dpu_enc;
1120 dpu_enc = to_dpu_encoder_virt(drm_enc);
1121 DPU_DEBUG_ENC(dpu_enc, "\n");
1147 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1154 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1155 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1158 dpu_enc->dsc_mask = dsc_mask;
1160 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
1161 dpu_enc->disp_info.intf_type == INTF_DP) {
1167 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1182 dpu_enc->connector = conn_state->connector;
1184 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1185 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1187 if (!dpu_enc->hw_pp[i]) {
1188 DPU_ERROR_ENC(dpu_enc,
1194 DPU_ERROR_ENC(dpu_enc,
1199 phys->hw_pp = dpu_enc->hw_pp[i];
1208 struct dpu_encoder_virt *dpu_enc = NULL;
1216 dpu_enc = to_dpu_encoder_virt(drm_enc);
1217 if (!dpu_enc || !dpu_enc->cur_master) {
1223 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1224 dpu_enc->cur_master->hw_mdptop &&
1225 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1226 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1227 dpu_enc->cur_master->hw_mdptop);
1229 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1231 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1232 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1233 unsigned bpc = dpu_enc->connector->display_info.bpc;
1235 if (!dpu_enc->hw_pp[i])
1237 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1244 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1246 mutex_lock(&dpu_enc->enc_lock);
1248 if (!dpu_enc->enabled)
1251 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1252 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1253 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1254 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1259 mutex_unlock(&dpu_enc->enc_lock);
1265 struct dpu_encoder_virt *dpu_enc = NULL;
1269 dpu_enc = to_dpu_encoder_virt(drm_enc);
1270 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1272 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
1274 mutex_lock(&dpu_enc->enc_lock);
1276 dpu_enc->commit_done_timedout = false;
1278 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1280 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);
1286 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1287 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1289 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1290 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1294 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1301 dpu_enc->enabled = true;
1304 mutex_unlock(&dpu_enc->enc_lock);
1310 struct dpu_encoder_virt *dpu_enc = NULL;
1315 dpu_enc = to_dpu_encoder_virt(drm_enc);
1316 DPU_DEBUG_ENC(dpu_enc, "\n");
1329 mutex_lock(&dpu_enc->enc_lock);
1330 dpu_enc->enabled = false;
1339 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1340 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1348 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1350 del_timer_sync(&dpu_enc->frame_done_timer);
1355 dpu_enc->connector = NULL;
1357 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1359 mutex_unlock(&dpu_enc->enc_lock);
1384 struct dpu_encoder_virt *dpu_enc = NULL;
1391 dpu_enc = to_dpu_encoder_virt(drm_enc);
1395 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1396 if (dpu_enc->crtc)
1397 dpu_crtc_vblank_callback(dpu_enc->crtc);
1398 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1423 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1426 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1428 WARN_ON(crtc && dpu_enc->crtc);
1429 dpu_enc->crtc = crtc;
1430 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1436 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1442 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1443 if (dpu_enc->crtc != crtc) {
1444 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1447 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1449 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1450 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1461 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1473 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1474 dpu_enc->crtc_frame_event_cb = frame_event_cb;
1475 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1476 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1483 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1490 if (!dpu_enc->frame_busy_mask[0]) {
1503 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1504 if (dpu_enc->phys_encs[i] == ready_phys) {
1506 dpu_enc->frame_busy_mask[0]);
1507 clear_bit(i, dpu_enc->frame_busy_mask);
1511 if (!dpu_enc->frame_busy_mask[0]) {
1512 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1513 del_timer(&dpu_enc->frame_done_timer);
1518 if (dpu_enc->crtc_frame_event_cb)
1519 dpu_enc->crtc_frame_event_cb(
1520 dpu_enc->crtc_frame_event_cb_data,
1524 if (dpu_enc->crtc_frame_event_cb)
1525 dpu_enc->crtc_frame_event_cb(
1526 dpu_enc->crtc_frame_event_cb_data, event);
1532 struct dpu_encoder_virt *dpu_enc = container_of(work,
1535 dpu_encoder_resource_control(&dpu_enc->base,
1538 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1644 struct dpu_encoder_virt *dpu_enc;
1649 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1661 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1675 * @dpu_enc: Pointer to virtual encoder structure
1677 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1686 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1689 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1690 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1703 set_bit(i, dpu_enc->frame_busy_mask);
1707 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1713 if (pending_flush && dpu_enc->cur_master) {
1715 &dpu_enc->base,
1716 dpu_enc->cur_master,
1720 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1722 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1727 struct dpu_encoder_virt *dpu_enc;
1737 dpu_enc = to_dpu_encoder_virt(drm_enc);
1738 disp_info = &dpu_enc->disp_info;
1740 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1741 phys = dpu_enc->phys_encs[i];
1748 if ((phys == dpu_enc->cur_master) &&
1755 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1765 if (!dpu_enc->cur_master)
1768 if (!dpu_enc->cur_master->ops.get_line_count) {
1795 DPU_DEBUG_ENC(dpu_enc,
1805 struct dpu_encoder_virt *dpu_enc;
1811 dpu_enc = to_dpu_encoder_virt(drm_enc);
1819 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1823 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1840 DPU_DEBUG_ENC(dpu_enc,
1899 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
1903 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
1915 hw_pp[i] = dpu_enc->hw_pp[i];
1916 hw_dsc[i] = dpu_enc->hw_dsc[i];
1919 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
1950 struct dpu_encoder_virt *dpu_enc;
1955 dpu_enc = to_dpu_encoder_virt(drm_enc);
1961 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1962 phys = dpu_enc->phys_encs[i];
1975 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1976 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1980 if (dpu_enc->dsc)
1981 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
1986 struct dpu_encoder_virt *dpu_enc;
1990 dpu_enc = to_dpu_encoder_virt(drm_enc);
1993 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1994 phys = dpu_enc->phys_encs[i];
2007 struct dpu_encoder_virt *dpu_enc;
2013 dpu_enc = to_dpu_encoder_virt(drm_enc);
2020 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
2021 mod_timer(&dpu_enc->frame_done_timer,
2025 _dpu_encoder_kickoff_phys(dpu_enc);
2028 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2029 phys = dpu_enc->phys_encs[i];
2085 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2088 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2095 hw_pp[i] = dpu_enc->hw_pp[i];
2096 hw_dsc[i] = dpu_enc->hw_dsc[i];
2108 struct dpu_encoder_virt *dpu_enc;
2110 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2130 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2131 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2133 dpu_enc->phys_encs[i]->hw_intf,
2139 dpu_enc->phys_encs[i]->hw_intf->idx);
2161 if (dpu_enc->dsc) {
2162 dpu_encoder_unprep_dsc(dpu_enc);
2163 dpu_enc->dsc = NULL;
2268 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2271 mutex_lock(&dpu_enc->enc_lock);
2272 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2273 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2280 atomic_read(&dpu_enc->frame_done_timeout_cnt));
2284 mutex_unlock(&dpu_enc->enc_lock);
2304 struct dpu_encoder_virt *dpu_enc,
2309 DPU_DEBUG_ENC(dpu_enc, "\n");
2315 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2316 ARRAY_SIZE(dpu_enc->phys_encs)) {
2317 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2318 dpu_enc->num_phys_encs);
2327 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2332 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2333 ++dpu_enc->num_phys_encs;
2338 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2343 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2344 ++dpu_enc->num_phys_encs;
2349 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2354 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2355 ++dpu_enc->num_phys_encs;
2359 dpu_enc->cur_slave = enc;
2361 dpu_enc->cur_master = enc;
2366 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2374 if (!dpu_enc) {
2375 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2379 dpu_enc->cur_master = NULL;
2383 phys_params.parent = &dpu_enc->base;
2384 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2391 dpu_enc->idle_pc_supported =
2394 mutex_lock(&dpu_enc->enc_lock);
2423 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2429 DPU_ERROR_ENC(dpu_enc,
2436 dpu_enc, &phys_params);
2438 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2443 mutex_unlock(&dpu_enc->enc_lock);
2450 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2452 struct drm_encoder *drm_enc = &dpu_enc->base;
2460 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2462 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2464 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2469 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2471 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1)
2476 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2496 struct dpu_encoder_virt *dpu_enc;
2499 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,
2501 if (IS_ERR(dpu_enc))
2502 return ERR_CAST(dpu_enc);
2504 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2506 spin_lock_init(&dpu_enc->enc_spinlock);
2507 dpu_enc->enabled = false;
2508 mutex_init(&dpu_enc->enc_lock);
2509 mutex_init(&dpu_enc->rc_lock);
2511 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2517 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2518 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
2519 timer_setup(&dpu_enc->frame_done_timer,
2522 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2524 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2526 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2528 DPU_DEBUG_ENC(dpu_enc, "created\n");
2530 return &dpu_enc->base;
2545 struct dpu_encoder_virt *dpu_enc = NULL;
2552 dpu_enc = to_dpu_encoder_virt(drm_enc);
2553 DPU_DEBUG_ENC(dpu_enc, "\n");
2555 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2556 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2562 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2563 dpu_enc->commit_done_timedout = true;
2586 struct dpu_encoder_virt *dpu_enc = NULL;
2593 dpu_enc = to_dpu_encoder_virt(drm_enc);
2594 DPU_DEBUG_ENC(dpu_enc, "\n");
2596 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2597 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2613 struct dpu_encoder_virt *dpu_enc = NULL;
2619 dpu_enc = to_dpu_encoder_virt(encoder);
2621 if (dpu_enc->cur_master)
2622 return dpu_enc->cur_master->intf_mode;
2624 if (dpu_enc->num_phys_encs)
2625 return dpu_enc->phys_encs[0]->intf_mode;
2633 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2635 return dpu_enc->dsc_mask;