disp/dpu1/dpu_encoder.c

1195 				"no ctl block assigned at idx: %d\n", i);
1551 	struct dpu_hw_ctl *ctl;
1560 	ctl = phys->hw_ctl;
1561 	if (!ctl->ops.trigger_flush) {
1568 	if (extra_flush_bits && ctl->ops.update_pending_flush)
1569 		ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1571 	ctl->ops.trigger_flush(ctl);
1573 	if (ctl->ops.get_pending_flush)
1574 		ret = ctl->ops.get_pending_flush(ctl);
1580 			pending_kickoff_cnt, ctl->idx,
1606 	struct dpu_hw_ctl *ctl;
1608 	ctl = phys_enc->hw_ctl;
1609 	if (ctl->ops.trigger_start) {
1610 		ctl->ops.trigger_start(ctl);
1611 		trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1645 	struct dpu_hw_ctl *ctl;
1650 	ctl = phys_enc->hw_ctl;
1653 	if (!ctl->ops.reset)
1656 	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1657 		      ctl->idx);
1659 	rc = ctl->ops.reset(ctl);
1661 		DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1679 	struct dpu_hw_ctl *ctl;
1685 	/* update pending counts and trigger kickoff ctl flush atomically */
1695 		ctl = phys->hw_ctl;
1708 		else if (ctl->ops.get_pending_flush)
1709 			pending_flush |= ctl->ops.get_pending_flush(ctl);
1730 	struct dpu_hw_ctl *ctl;
1743 		ctl = phys->hw_ctl;
1744 		if (ctl->ops.clear_pending_flush)
1745 			ctl->ops.clear_pending_flush(ctl);
1747 		/* update only for command mode primary ctl */
1750 		    && ctl->ops.trigger_pending)
1751 			ctl->ops.trigger_pending(ctl);
1873 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
1895 	if (ctl->ops.update_pending_flush_dsc)
1896 		ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
1904 	struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
1944 		dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
2044 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2060 			phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2064 			phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2068 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2081 	if (ctl->ops.update_pending_flush_dsc)
2082 		ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2089 	struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2099 			dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2105 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2112 	phys_enc->hw_ctl->ops.reset(ctl);
2128 			phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2148 			phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2178 	if (ctl->ops.reset_intf_cfg)
2179 		ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2181 	ctl->ops.trigger_flush(ctl);
2182 	ctl->ops.trigger_start(ctl);
2183 	ctl->ops.clear_pending_flush(ctl);