disp/dpu1/dpu_crtc.c

441 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
469 					   mixer, cstate->num_mixers,
477 						   mixer, cstate->num_mixers,
484 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
508 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
509 	struct dpu_crtc_mixer *mixer = cstate->mixers;
517 	for (i = 0; i < cstate->num_mixers; i++) {
529 	for (i = 0; i < cstate->num_mixers; i++) {
717 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
719 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
722 	for (i = 0; i < cstate->num_mixers; i++) {
723 		struct drm_rect *r = &cstate->lm_bounds[i];
761 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
762 	struct dpu_crtc_mixer *mixer = cstate->mixers;
772 	for (i = 0; i < cstate->num_mixers; i++) {
795 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
817 	if (unlikely(!cstate->num_mixers))
841 	struct dpu_crtc_state *cstate;
852 	cstate = to_dpu_crtc_state(crtc->state);
872 	if (unlikely(!cstate->num_mixers))
900 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
906 	kfree(cstate);
936 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
943 	if (unlikely(!cstate->num_mixers))
984 	struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
989 	if (cstate)
990 		__drm_atomic_helper_crtc_reset(crtc, &cstate->base);
1001 	struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
1003 	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
1004 	if (!cstate) {
1010 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
1012 	return &cstate->base;
1018 	const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1021 	for (i = 0; i < cstate->num_mixers; i++) {
1022 		drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
1023 		drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
1024 		if (cstate->mixers[i].hw_dspp)
1025 			drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
1035 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
1097 	memset(cstate->mixers, 0, sizeof(cstate->mixers));
1098 	cstate->num_mixers = 0;
1101 	cstate->bw_control = false;
1102 	cstate->bw_split_vote = false;
1154 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
1156 	struct drm_crtc *crtc = cstate->crtc;
1159 	if (cstate->self_refresh_active)
1162 	drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
1177 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
1190 		memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1200 	if (cstate->num_mixers)
1276 	struct dpu_crtc_state *cstate;
1284 	cstate = to_dpu_crtc_state(crtc->state);
1287 	out_width = mode->hdisplay / cstate->num_mixers;
1294 	for (i = 0; i < cstate->num_mixers; ++i) {
1295 		m = &cstate->mixers[i];