msm/adreno/a6xx_gmu.c

14 #include "a6xx_gpu.h"
22 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
23 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
112 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
113 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
172 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
173 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
206 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
207 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
518 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
519 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
655 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
656 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
714 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
715 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
770 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
771 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
784 		a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
928 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
929 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
950 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
951 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
958 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1015 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
1017 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1019 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1067 		status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
1129 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1130 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1148 		a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
1187 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1189 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1190 	struct msm_gpu *gpu = &a6xx_gpu->base.base;
1238 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1239 	struct drm_device *dev = a6xx_gpu->base.base.dev;
1394 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1395 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1444 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1445 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1534 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1536 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1537 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1594 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1597 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1657 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1659 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1660 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;