drm/meson/meson_vclk.c

491 				      unsigned int frac, unsigned int od1,
498 		if (frac)
500 				     0x00004000 | frac);
519 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
542 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
547 			if (frac < 0x10000) {
643 	unsigned int frac;
659 	frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
661 	if (frac_m > frac)
663 	frac -= frac_m;
665 	return min((u16)frac, (u16)(frac_max - 1));
670 					   unsigned int frac)
676 		if (frac >= HDMI_FRAC_MAX_GXBB)
683 		if (frac >= HDMI_FRAC_MAX_GXL)
689 		if (frac >= HDMI_FRAC_MAX_G12A)
699 				       unsigned int *frac,
707 		*frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
709 		DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",
710 				 freq, *m, *frac, *od);
712 		if (meson_hdmi_pll_validate_params(priv, *m, *frac))
723 	unsigned int od, m, frac;
735 	if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
746 	unsigned int od, m, frac, od1, od2, od3;
748 	if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
759 		DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
760 				 pll_freq, m, frac, od1, od2, od3);
762 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
814 	unsigned int m = 0, frac = 0;
831 			frac = vic_alternate_clock ? 0xd02 : 0xe00;
835 			frac = vic_alternate_clock ? 0xe8f : 0;
839 			frac = vic_alternate_clock ? 0xa05 : 0xc00;
843 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
849 			frac = vic_alternate_clock ? 0x281 : 0x300;
853 			frac = vic_alternate_clock ? 0x347 : 0;
857 			frac = vic_alternate_clock ? 0x102 : 0x200;
861 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
866 			frac = vic_alternate_clock ? 0x140b4 : 0x18000;
870 			frac = vic_alternate_clock ? 0x1a3ee : 0;
874 			frac = vic_alternate_clock ? 0x8148 : 0x10000;
878 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);