drm/meson/meson_dw_hdmi.c

18 #include <drm/bridge/dw_hdmi.h>
127 	unsigned int	(*top_read)(struct meson_dw_hdmi *dw_hdmi,
129 	void		(*top_write)(struct meson_dw_hdmi *dw_hdmi,
131 	unsigned int	(*dwc_read)(struct meson_dw_hdmi *dw_hdmi,
133 	void		(*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
149 	struct dw_hdmi *hdmi;
153 static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi,
156 	return of_device_is_compatible(dw_hdmi->dev->of_node, compat);
161 static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi,
170 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
171 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
174 	data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
175 	data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
182 static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi,
185 	return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
188 static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
196 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
197 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
200 	writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
205 static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi,
208 	writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
212 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
217 	unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr);
222 	dw_hdmi->data->top_write(dw_hdmi, addr, data);
225 static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
234 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
235 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
238 	data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
239 	data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
246 static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi,
249 	return readb(dw_hdmi->hdmitx + addr);
252 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
260 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
261 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
264 	writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
269 static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi,
272 	writeb(data, dw_hdmi->hdmitx + addr);
276 static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi,
281 	unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr);
286 	dw_hdmi->data->dwc_write(dw_hdmi, addr, data);
292 static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
296 	struct meson_drm *priv = dw_hdmi->priv;
302 	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
303 	    dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) {
321 	} else if (dw_hdmi_is_compatible(dw_hdmi,
336 	} else if (dw_hdmi_is_compatible(dw_hdmi,
357 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
359 	struct meson_drm *priv = dw_hdmi->priv;
372 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
376 	struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
378 	struct meson_drm *priv = dw_hdmi->priv;
393 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
395 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
398 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
400 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
405 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
407 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
410 	meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
420 	meson_dw_hdmi_phy_reset(dw_hdmi);
421 	meson_dw_hdmi_phy_reset(dw_hdmi);
422 	meson_dw_hdmi_phy_reset(dw_hdmi);
457 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
460 	struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
461 	struct meson_drm *priv = dw_hdmi->priv;
466 	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
467 	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
470 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
473 	struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
475 	return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
479 static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi,
482 	struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
485 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
489 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
493 	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN,
507 	struct meson_dw_hdmi *dw_hdmi = dev_id;
510 	stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
511 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
515 		dw_hdmi->irq_stat = stat;
531 	struct meson_dw_hdmi *dw_hdmi = dev_id;
532 	u32 stat = dw_hdmi->irq_stat;
541 		dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
544 		drm_helper_hpd_irq_event(dw_hdmi->bridge->dev);
545 		drm_bridge_hpd_notify(dw_hdmi->bridge,
558 	struct meson_dw_hdmi *dw_hdmi = context;
560 	*result = dw_hdmi->data->dwc_read(dw_hdmi, reg);
569 	struct meson_dw_hdmi *dw_hdmi = context;
571 	dw_hdmi->data->dwc_write(dw_hdmi, reg, val);