drm/mediatek/mtk_ethdr.c

87 	"mixer",
152 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
164 		mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
176 	mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
177 		      mixer->regs, MIX_L_SRC_SIZE(idx));
178 	mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
179 	mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
181 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
195 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
214 	mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
215 	mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
216 	mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
217 	mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
218 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
220 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
222 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
224 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
226 	mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
228 		      &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
229 	mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
239 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
241 	writel(1, mixer->regs + MIX_EN);
247 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
249 	writel(0, mixer->regs + MIX_EN);
250 	writel(1, mixer->regs + MIX_RST);
252 	writel(0, mixer->regs + MIX_RST);