drm/mediatek/mtk_disp_ovl.c

235 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,
238 	mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,
244 				  struct cmdq_pkt *cmdq_pkt)
263 	mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,
269 		    unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
274 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
276 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
278 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
279 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
324 		      struct cmdq_pkt *cmdq_pkt)
331 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
342 	mtk_ddp_write(cmdq_pkt, gmc_value,
344 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
349 		       struct cmdq_pkt *cmdq_pkt)
353 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
355 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
399 			  struct cmdq_pkt *cmdq_pkt)
423 		mtk_ovl_layer_off(dev, idx, cmdq_pkt);
442 		mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);
444 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
446 	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
448 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
450 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
452 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
456 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
458 		mtk_ddp_write_relaxed(cmdq_pkt,
461 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
464 		mtk_ddp_write_relaxed(cmdq_pkt,
469 	mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
470 	mtk_ovl_layer_on(dev, idx, cmdq_pkt);