drm/mediatek/mtk_cec.c

62 static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
65 	void __iomem *reg = cec->regs + offset;
73 static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
76 	void __iomem *reg = cec->regs + offset;
84 static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
87 	u32 tmp = readl(cec->regs + offset) & ~mask;
90 	writel(tmp, cec->regs + offset);
97 	struct mtk_cec *cec = dev_get_drvdata(dev);
100 	spin_lock_irqsave(&cec->lock, flags);
101 	cec->hdmi_dev = hdmi_dev;
102 	cec->hpd_event = hpd_event;
103 	spin_unlock_irqrestore(&cec->lock, flags);
108 	struct mtk_cec *cec = dev_get_drvdata(dev);
111 	status = readl(cec->regs + RX_EVENT);
116 static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
118 	mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
119 	mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
121 	mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
126 static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
128 	mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
131 static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
133 	mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
136 static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
138 	mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
139 	mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
141 	mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
144 	mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
146 	mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
147 	mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
151 static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
157 	spin_lock_irqsave(&cec->lock, flags);
158 	hpd_event = cec->hpd_event;
159 	hdmi_dev = cec->hdmi_dev;
160 	spin_unlock_irqrestore(&cec->lock, flags);
169 	struct mtk_cec *cec = dev_get_drvdata(dev);
172 	mtk_cec_clear_htplg_irq(cec);
175 	if (cec->hpd != hpd) {
177 			cec->hpd, hpd);
178 		cec->hpd = hpd;
179 		mtk_cec_hpd_event(cec, hpd);
187 	struct mtk_cec *cec;
190 	cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
191 	if (!cec)
194 	platform_set_drvdata(pdev, cec);
195 	spin_lock_init(&cec->lock);
197 	cec->regs = devm_platform_ioremap_resource(pdev, 0);
198 	if (IS_ERR(cec->regs)) {
199 		ret = PTR_ERR(cec->regs);
200 		dev_err(dev, "Failed to ioremap cec: %d\n", ret);
204 	cec->clk = devm_clk_get(dev, NULL);
205 	if (IS_ERR(cec->clk)) {
206 		ret = PTR_ERR(cec->clk);
207 		dev_err(dev, "Failed to get cec clock: %d\n", ret);
211 	cec->irq = platform_get_irq(pdev, 0);
212 	if (cec->irq < 0)
213 		return cec->irq;
215 	ret = devm_request_threaded_irq(dev, cec->irq, NULL,
220 		dev_err(dev, "Failed to register cec irq: %d\n", ret);
224 	ret = clk_prepare_enable(cec->clk);
226 		dev_err(dev, "Failed to enable cec clock: %d\n", ret);
230 	mtk_cec_htplg_irq_init(cec);
231 	mtk_cec_htplg_irq_enable(cec);
238 	struct mtk_cec *cec = platform_get_drvdata(pdev);
240 	mtk_cec_htplg_irq_disable(cec);
241 	clk_disable_unprepare(cec->clk);
245 	{ .compatible = "mediatek,mt8173-cec", },
254 		.name = "mediatek-cec",